Viterbi Decoder Parallel Backtracking for Faster Traceback
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Solution Overview
Problem
Conventional Viterbi decoding methods are limited by their sequential processing nature, which restricts speed improvements regardless of available hardware resources, making it challenging to achieve high-performance decoding at low silicon costs for high data rate communications.
Innovation Solution
The implementation of fast parallel backtracking in Viterbi decoding, where multiple processing steps are executed in parallel, allowing the output of one step to inform and guide subsequent steps, thereby increasing processing efficiency without requiring additional hardware resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential processing is used in Viterbi backtracking, then hardware complexity is reduced, but processing speed cannot be improved
Solution Approach 1:
The patent divides the backtracking process into multiple independent segments or steps that can be executed in parallel. Each processing step handles a specific portion of the traceback operation, allowing simultaneous execution of multiple steps without increasing overall hardware complexity. This segmentation enables speed improvement while maintaining manageable device complexity.
Solution Approach 2:
The patent transitions from sequential (one-dimensional) processing to parallel processing by introducing a temporal dimension. Multiple processing steps that would traditionally execute one after another are reorganized to execute simultaneously, effectively adding a parallel processing dimension to the architecture. This allows speed improvement without proportionally increasing hardware resources.
2Productivity
If parallel processing is applied to Viterbi backtracking, then processing speed increases, but hardware resources are consumed
Solution Approach 1:
The patent designs processing units that can perform multiple functions across different parallel steps. The same hardware resources are reused across multiple processing steps through time-multiplexing and functional reuse, reducing the total hardware resources required for parallel processing. This multi-functionality allows high decoding efficiency without proportionally increasing hardware resources.
Solution Approach 2:
The patent performs preliminary organization and preparation of data structures and processing pipelines before parallel execution begins. By pre-arranging the computational workflow and data flow paths, the system enables efficient parallel processing without requiring excessive hardware resources during execution. This preliminary action optimizes resource utilization for parallel operations.
Data Source
AI summary
A Viterbi traceback processing method, system, and apparatus are provided wherein a first Viterbi traceback processing operation (MUX 514) is performed on a first survivor path metric (TMV1) by selecting, in response to a back track state (INDEX 0), a first output data bit (Ti1) for the first survivor path metric, wherein a plurality of Viterbi traceback processing operations (MUX 512, 513) are performed on respective portions of an additional survivor path metric (TMV2A, TMV2B) by selecting, in response to a shifted back track state (INDEX 1), candidate data bits (Tn1, Tn2) for the additional survivor path metric, wherein a multiplexer (MUX 518) controlled by the first output data bit selects between the candidate data bits to generate an additional output data bit (Ti2) for the additional survivor path metric such that the Viterbi traceback processing operations are performed in parallel to produce the output data bits.