Viterbi Pretraceback Initialization for Lower BER Decoding

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Solution Overview

Problem

Viterbi decoders suffer from poor bit error rate (BER) due to incorrect traceback initialization, which affects the performance of forward error correction systems in wireless communications and other applications.

Innovation Solution

The solution involves forcing unused ACS units to generate decision bits of 0 for the top rail and 1 for the bottom rail, modifying the final maximum state index, and using this index to initialize the traceback shift register correctly, ensuring proper pretraceback and traceback logic initialization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the traceback is not initialized correctly, then the traceback results can fail, but correcting the initialization requires modifying the pretraceback logic and final maximum state index

Engineering Contradiction:

Improvetraceback initialization correctnessVSAvoidpretraceback logic complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forcing unused ACS units to generate decision bits (0 for top rail, 1 for bottom rail) before the actual traceback process. This pre-initialization of decision bits and modification of the final maximum state index ensures that the traceback shift register is correctly initialized, preventing traceback failures without requiring complex runtime corrections

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes parameters by modifying the final maximum state index and forcing specific decision bit values from unused ACS units. These parameter modifications transform the initialization process, ensuring that the traceback shift register receives correct initial values (k-1 ones) without increasing structural complexity

Inventive Principle:

Principle #35Parameter changes

2Reliability

If unused ACS units are forced to generate decision bits, then traceback initialization is corrected, but additional logic is required to modify the final maximum state index

Engineering Contradiction:

Improvebit error rate performanceVSAvoidinitialization logic complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by forcing unused ACS units to output specific decision bit values (0 for top rail, 1 for bottom rail) and modifying the final maximum state index accordingly. These parameter modifications improve BER performance by ensuring correct traceback initialization without requiring fundamental architectural changes

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements self-service by using the unused ACS units themselves to generate the required decision bits for initialization. Instead of adding separate initialization logic, the system repurposes existing unused resources (unused ACS units) to provide the necessary initialization data, reducing overall system complexity

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS7594162B2Viterbi pretraceback for partial cascade processing

Publication Date: 2009.09.22 TEXAS INSTRUMENTS INC

AI summary

This invention modifies Viterbi decoding to improve BER. Within the state metric unit cascade block, this invention forces the unused ACS units decision bits to a 0 for the top rail and a 1 for the bottom rail. This invention modifies the final maximum state index with the selected decision bits from the unused ACS units. This invention uses the modified final maximum state index as the initial conditions for the k−1 traceback shift register. This invention also uses the final maximum state index to mask the generated pretraceback decision bits generated from the last block of ACS units.