Viterbi Decoder Register Exchange With Cyclic Bit Expansion
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Solution Overview
Problem
Existing Viterbi decoders in register exchange methods face challenges with increased power consumption and the number of required registers, especially when dealing with longer unit packets, due to frequent register value transitions and difficulties in determining initial states in tail-biting convolutional encoding.
Innovation Solution
A Viterbi decoder configuration that includes a receiving buffer, a bit sequence expansion unit, a Viterbi decoding unit, an end bit sequence selector, and a rearranging unit, which performs Viterbi decoding using a modified register exchange method by exchanging pointers instead of register values and cyclically adding encoded bit sequences to simplify the decoding process and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional register exchange method is used for Viterbi decoding, then the decoding process can be completed, but the power consumption increases and the number of required registers increases due to frequent register value transitions
Solution Approach 1:
The patent divides the encoded bit sequence into multiple segments and processes them through multiple stages of Viterbi decoding. By segmenting the decoding process into sequential stages rather than processing the entire sequence at once, the register exchange operations are reduced in frequency, thereby lowering power consumption while maintaining decoding reliability through systematic multi-stage processing
Solution Approach 2:
The patent performs preliminary processing by cyclically adding encoded bit sequences before the main Viterbi decoding operation. This preliminary action prepares the data in advance, allowing the main decoding process to operate more efficiently with fewer register exchanges, thus reducing power consumption while ensuring accurate decoding results
2Reliability
If the conventional register exchange method is used for Viterbi decoding, then the decoding can be performed, but the number of required registers increases due to the need to store extensive register values
Solution Approach 1:
The patent segments the Viterbi decoding process into multiple stages, where each stage processes a portion of the encoded bit sequence. This segmentation allows registers to be reused across stages rather than requiring separate registers for entire sequences, significantly reducing the total number of registers needed while maintaining decoding reliability through systematic stage-by-stage processing
Solution Approach 2:
The patent employs a strategy where register values from previous stages are discarded after their utility is exhausted and then recovered/reused in subsequent stages. This approach minimizes the number of active registers required at any given time while ensuring that necessary decoding information is preserved and reused efficiently throughout the multi-stage process
3Reliability
If zero-tail convolutional encoding is used, then error correction capability is improved, but the data rate is reduced due to additional zero tail sequence
Solution Approach 1:
The patent applies partial zero-tail sequencing by adding zero tail sequences selectively rather than always adding the full K-1 zero bits. By applying zero-tail encoding partially or conditionally, the system maintains improved error correction capability where needed while avoiding unnecessary data rate reduction, thus balancing reliability and productivity
4Productivity
If tail-biting convolutional encoding is used, then data rate is improved by eliminating zero tail sequence, but the initial state determination becomes difficult
Solution Approach 1:
The patent performs preliminary processing by cyclically adding the encoded bit sequence before Viterbi decoding. This preliminary action creates a known reference structure that facilitates initial state determination in tail-biting convolutional encoding, allowing the decoder to correctly identify the starting state without requiring additional overhead bits, thus maintaining high data rate while solving the initial state detection problem
Data Source
AI summary
The present invention relates to a Viterbi decoder and a Viterbi decoding method in a register exchange method. The Viterbi decoder receives an encoded bit sequence of a convolutional encoding method from a channel, generates an expanded encoded bit sequence by cyclically adding a part of the encoded bit sequence or the entire encoded bit sequence to the encoded bit sequence more than one time, performs a Viterbi decoding operation in a register exchange method, and generates decoded data. In addition, the Viterbi decoder selects an end bit sequence corresponding to the number of the unit of encoded bits among the decoded data, rearranges an order of the end bit sequence, and generates final decoded data.