Viterbi Survivor Memory Architecture for Low-Latency Parallel Decoding
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Solution Overview
Problem
Current methods for decoding convolutionally encoded telecommunications signals face challenges in efficiency, power consumption, and latency, particularly in mobile systems, due to high decoding complexity and simultaneous read/write access requirements in register exchange processes, and increased latency in trace-back approaches.
Innovation Solution
The proposed solution involves parallel processing of trellis searches, trace-forward, and trace-back operations using multiple dedicated memory registers and multiplexers, allowing for simultaneous storage and output of decision bits in different memory types, and implementing tail-biting checks to optimize memory usage and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If register exchange approach is used for Viterbi decoding, then decoding speed is improved, but power consumption increases due to simultaneous read and write access to all L×N registers
Solution Approach 1:
The patent segments the L×N register array into multiple smaller sub-arrays or groups, allowing the decoding process to access only a subset of registers at each time step. This segmentation reduces the number of simultaneous read/write operations required, thereby lowering power consumption while maintaining decoding throughput through pipelined or parallel processing of different register segments.
Solution Approach 2:
The patent implements periodic access patterns to the register array, where registers are accessed in a cyclic or alternating manner rather than all at once. This periodic action allows the system to process data in phases, reducing peak power consumption by spreading read/write operations over multiple clock cycles while maintaining overall decoding speed through efficient scheduling.
2Quantity of substance
If trace-back approach is used for Viterbi decoding, then memory requirements are reduced, but latency increases due to inverse-ordered output requiring LIFO processing
Solution Approach 1:
The patent inverts the traditional trace-back approach by implementing trace-forward logic that generates output in natural chronological order rather than reverse order. This inversion eliminates the need for LIFO processing and associated latency, while still maintaining reduced memory requirements by storing only essential survivor path information in a streamlined format.
Solution Approach 2:
The patent performs preliminary organization of decoded data during the trellis search phase, pre-positioning information in a format that enables direct forward sequential output. This preliminary action eliminates the need for post-decoding reordering operations, reducing latency while maintaining efficient memory usage through optimized data placement strategies.
3Reliability
If larger constraint length is used in convolutional encoder, then protection against noise is improved, but decoding complexity increases quadratically
Solution Approach 1:
The patent segments the trellis search process into independent or semi-independent stages that can be processed in parallel. By dividing the complex decoding task associated with larger constraint lengths into manageable segments, the system achieves quadratic complexity reduction while maintaining the noise protection benefits of larger constraint lengths through coordinated processing of segmented data.
Solution Approach 2:
The patent introduces parallel processing dimensions to the decoding architecture, using multiple processing units operating simultaneously on different portions of the trellis structure. This dimensional expansion allows the system to handle larger constraint lengths with reduced per-unit complexity, achieving overall quadratic complexity reduction through parallelism while maintaining high reliability.
Data Source
AI summary
In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.