Viterbi Survivor Memory Architecture for Low-Latency Decoding
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Solution Overview
Problem
Current methods for decoding convolutionally encoded telecommunications data streams face challenges in efficiency, power consumption, and latency, particularly in mobile systems, due to high decoding complexity and simultaneous read/write access requirements in register exchange approaches, and increased latency in trace-back methods.
Innovation Solution
The proposed solution involves parallel processing of trellis searches, trace-forward, and trace-back operations using multiple dedicated memory registers and multiplexers, allowing for parallel execution of trace-forward processes and storage of decision bits in both registers and RAM, with a tail-biting criterion to optimize memory usage and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If register exchange method is used to store Viterbi survivor paths, then decoding accuracy is maintained, but power consumption and device complexity increase due to simultaneous read/write access requirements
Solution Approach 1:
The patent divides the survivor memory into multiple banks (first bank and second bank) that can be independently accessed. This segmentation allows parallel read and write operations to occur simultaneously in different banks, eliminating the need for sequential access that causes power consumption spikes while maintaining decoding accuracy through proper distribution of memory operations across banks.
2Quantity of substance
If trace-back approach is used to decode Viterbi-encoded data, then memory requirements are reduced, but latency increases due to inverse-ordered output requiring LIFO processing
Solution Approach 1:
The patent performs preliminary actions by storing not only decision bits but also path trace information and state addresses in the survivor memory during the Viterbi decoding process. This preliminary storage of trace information eliminates the need for separate LIFO processing later, as the output can be generated in correct order directly from the stored trace data, reducing latency while maintaining reduced memory requirements.
3Loss of time
If Modified Register Exchange method is used with multiple trace-forward units, then decoding latency is reduced, but device complexity and power consumption increase
Solution Approach 1:
The patent designs the survivor memory banks to serve multiple functions: storing decision bits, storing path trace information, and storing state addresses. This multi-functionality eliminates the need for separate dedicated structures for each purpose, reducing device complexity while maintaining the low latency achieved through parallel trace-forward operations.
Solution Approach 2:
The patent merges the storage of decision bits, path traces, and state addresses into a unified bank structure that can be simultaneously accessed for multiple purposes. This combining of storage functions into single banks reduces the overall number of memory structures needed and simplifies the control logic, thereby reducing device complexity while maintaining low decoding latency.
Data Source
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AI summary
In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.