Viterbi Traceback Circuit for Constant-Cycle Channel Decoding
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Solution Overview
Problem
Current DSP implementations of Viterbi decoders, particularly the traceback stage, are inefficient due to sequential operations and high power consumption, especially for larger constraint lengths, leading to increased DSP cycles and memory accesses.
Innovation Solution
A hardware enhancement module that performs a single iteration of traceback in one DSP cycle, regardless of the number of states, by utilizing a generalized traceback circuit with an eight-bit shift register, 16-bit traceback vector register, and optimized memory addressing, reducing the need for large multiplexers and memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional DSP implementation of traceback operation is used, then the decoder can handle various constraint lengths, but the number of DSP cycles per decoded bit increases substantially with larger constraint lengths
Solution Approach 1:
The traceback vector is segmented into multiple 16-bit words stored in memory, with each word containing a portion of the traceback bits. The segmented approach allows efficient memory access and reduces the computational burden per cycle, enabling constant DSP cycles regardless of constraint length
Solution Approach 2:
The patent introduces a new dimension of organization by storing the traceback vector as an array of 16-bit words in memory rather than as a simple sequential register. This dimensional reorganization allows parallel access to multiple traceback bits through word-level memory operations, achieving O(1) complexity independent of constraint length
2Productivity
If conventional Viterbi hardware accelerators are used, then traceback computation is performed in one cycle per decoded bit, but a substantial amount of hardware support is required for large constraint lengths
Solution Approach 1:
The patent introduces an intermediary memory structure that stores the traceback vector in a compact 16-bit word format. This memory intermediary eliminates the need for complex combinatorial logic and large multiplexers by providing direct access to traceback bits through simple memory read operations, reducing hardware complexity while maintaining one-cycle performance
Solution Approach 2:
The patent replaces the mechanical/combinatorial system of large multiplexers and complex routing logic with a memory-based system. Instead of using physical multiplexing hardware to select traceback bits, the system uses memory addressing to access the same data, significantly reducing hardware complexity for large constraint lengths
3Adaptability or versatility
If large multiplexers and multi-cycle loading of traceback vector are used, then the decoder can support large constraint lengths, but memory accesses and power consumption increase
Solution Approach 1:
The traceback vector is segmented into 16-bit words that can be efficiently stored and accessed in memory. This segmentation allows the entire vector to be loaded in a single memory cycle regardless of size, and individual bits can be accessed through simple address decoding, reducing power consumption compared to bit-by-bit access or large multiplexer operations
Solution Approach 2:
The patent changes the organizational parameter of the traceback vector from individual bits to 16-bit words. This parameter change enables more efficient memory utilization and access patterns, reducing the number of memory cycles required and thereby reducing dynamic power consumption in the memory subsystem
Data Source
AI summary
Apparatus, system, and method for scalable traceback techniques for channel decoding are described.