Viterbi Traceback Architecture With Low-Power Shift Register Decoding
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Solution Overview
Problem
Existing Viterbi decoding techniques face challenges in achieving both low power consumption and low latency, with current methods either consuming high power or incurring significant latency, which is undesirable in digital communications and storage technologies.
Innovation Solution
A low power Viterbi trace back architecture is introduced, utilizing a sliding 1-bit shift register and a multiplexer chain to reduce power consumption while maintaining minimal latency, by allowing only a single register to be clocked each cycle and propagating decoded values through a combinational logic structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional register exchange technique is used, then decoding speed is maintained, but power consumption increases
Solution Approach 1:
The trace back operation is segmented into multiple stages, with only one stage active at a time. The trace back logic is divided into P stages corresponding to P register elements, where each stage processes one bit of the decision output. This segmentation allows the system to activate only a subset of registers and logic at any given time, reducing overall power consumption while maintaining the decoding function.
Solution Approach 2:
The trace back operation is performed periodically across P clock cycles rather than simultaneously. Each clock cycle activates one stage of the trace back logic corresponding to one bit of the decision output. This periodic activation pattern reduces instantaneous power consumption and average power usage compared to simultaneous activation, while the total latency increases only by the survivor path length P.
2Use of energy by moving object
If trace back technique is used, then power consumption is reduced, but latency increases substantially
Solution Approach 1:
The trace back logic is segmented into P stages, each handling one bit of the decision output. This segmentation allows parallel preparation of trace back values across stages while only one stage is actively switching at a time, reducing power consumption. The segmented structure enables the system to maintain decoding speed by preparing values in parallel across stages while activating only necessary logic periodically.
Solution Approach 2:
Trace back values are pre-computed and stored in register elements before being actively used. The register elements hold the decision outputs and trace back information ready for periodic activation. This preliminary action allows the system to reduce power consumption during the active trace back phase while maintaining fast decoding speed by having values ready for immediate processing when activated.
Data Source
AI summary
A method of obtaining a Viterbi decoded value is disclosed. A decision output is stored to one of a plurality of buffer elements, wherein at least one other buffer element in the plurality is not changing; and data is exposed in the buffer element. A plurality of stored decision outputs is obtained from the plurality of buffers elements. The obtained plurality of stored decision outputs is processed to obtain a Viterbi decoded value.