VIVT Cache TLB Index Valid Bit for Selective Invalidation
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Solution Overview
Problem
Conventional VIVT cache implementations face inefficiencies in cache line invalidation, where entire caches are often invalidated even when only a single TLB entry needs to be updated, leading to unnecessary data loss and performance issues during context switches between applications.
Innovation Solution
Implementing a TLB index valid bit in each cache line of a VIVT cache, which is cleared when the associated TLB entry is evicted or replaced, and using an invalidate vector to track pending invalidate instructions, allowing for selective cache line invalidation based on context synchronization events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire VIVT cache is invalidated during a TLB invalidate operation, then all cache lines are ensured to be consistent with the updated translation, but unnecessary cache lines are also invalidated leading to data loss and performance degradation
Solution Approach 1:
The patent segments the cache invalidation process by introducing a TLB index valid bit in each cache line, allowing individual cache lines to be tracked and invalidated separately based on their association with specific TLB entries. This enables selective invalidation of only those cache lines whose translations have changed, rather than invalidating the entire cache.
Solution Approach 2:
The patent applies local quality by making each cache line have its own TLB index valid bit that reflects the validity status of its associated TLB entry. This allows different cache lines to have different validity states independently, enabling precise control over which cache lines need invalidation based on local translation changes.
2Productivity
If a VIVT cache is implemented to appear as a PIPT cache to software, then context switch performance is improved by avoiding entire cache invalidation, but it becomes difficult to determine which specific cache lines need invalidation when a TLB entry is updated
Solution Approach 1:
The patent performs preliminary action by setting the TLB index valid bit in each cache line when the associated TLB entry is populated. This pre-establishes the mapping relationship between cache lines and TLB entries, so that when a TLB entry is evicted or updated, the corresponding cache lines can be quickly identified and invalidated without requiring complex tracking mechanisms.
3Measurement precision
If the TLB index valid bit is cleared when the associated TLB entry is evicted, then precise invalidation can be performed, but additional bookkeeping and tracking logic is required to maintain the valid bit state
Solution Approach 1:
The patent applies self-service by having the TLB index valid bit automatically updated based on the validity status of the associated TLB entry. When a TLB entry is populated, the corresponding cache line's valid bit is set; when the TLB entry is evicted, the valid bit is automatically cleared. This self-updating mechanism reduces the need for complex external tracking logic while maintaining precise invalidation capability.
Data Source
AI summary
A translation lookaside buffer (TLB) index valid bit is set in a first line of a virtually indexed, virtually tagged (VIVT) cache. The first line of the VIVT cache is associated with a first TLB entry which stores a virtual address to physical address translation for the first cache line. The TLB index valid bit of the first line is cleared upon determining that the translation is no longer stored in the first TLB entry. An indication of a received invalidation instruction is stored. When a context synchronization instruction is received, the first line of the VIVT cache is cleared based on the TLB index valid bit being cleared and the stored indication of the invalidate instruction.