VLAN-Aware Clock Hierarchy for Network Synchronization

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Solution Overview

Problem

Conventional Precision Time Protocol (PTP) processing does not synchronize clocks across different Virtual Local Area Networks (VLANs), leading to latency and delay variations in networked computer-based devices.

Innovation Solution

A VLAN-aware clock synchronization technique that establishes a master/slave timing tree across devices in different VLANs, using the Precision Time Protocol (PTP) to synchronize clocks by determining the best clock data for each VLAN and setting port states accordingly, allowing synchronization across multiple VLANs on a trunk port.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional PTP processing is used, then clock synchronization is achieved within the same VLAN, but clocks cannot be synchronized across different VLANs leading to latency and delay variations

Engineering Contradiction:
Improveclock synchronization accuracyVSAvoidVLAN compatibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the clock synchronization process by creating separate timing trees for each VLAN while maintaining a hierarchical structure. Each VLAN processes PTP messages independently through its own boundary clocks, allowing synchronization within VLAN boundaries while preventing cross-VLAN interference. This segmentation enables multi-VLAN support without compromising the reliability of individual VLAN synchronizations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces boundary clocks as intermediary devices between different VLANs. These boundary clocks receive PTP synchronization messages from grandmaster clocks, process them independently for each connected VLAN, and distribute synchronized time references to slave clocks within each VLAN. This intermediary approach enables clock synchronization across multiple VLANs while maintaining isolation and preventing latency variations from propagating across VLAN boundaries.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If a single timing tree is used for all VLANs, then simplified clock synchronization is achieved, but latency and delay variations occur across different VLANs

Engineering Contradiction:
Improvetiming tree structureVSAvoidnetwork latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent divides the network into multiple independent timing trees, each corresponding to a specific VLAN. This segmentation allows each VLAN to have its own optimized synchronization path from grandmaster to slave clocks, eliminating the latency and delay variations that would occur in a shared timing tree. The complexity is managed through automated discovery and configuration of these segmented trees.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements local quality optimization by allowing each VLAN to have its own timing tree structure optimized for its specific network characteristics. Each boundary clock can independently adjust synchronization parameters for its connected VLAN, ensuring minimal latency and delay variations within each local VLAN environment while maintaining overall system coherence.

Inventive Principle:
Principle #3Local quality

3Ease of operation

If clocks are synchronized without VLAN awareness, then simpler processing is achieved, but accurate time references cannot be maintained across devices in different VLANs

Engineering Contradiction:
Improvesynchronization processingVSAvoidtime reference accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent employs boundary clocks as VLAN-aware intermediaries that automatically discover and process PTP messages for each connected VLAN. These intermediaries maintain separate synchronization states for each VLAN, ensuring accurate time references are distributed correctly within each VLAN context. The processing remains relatively simple for each individual VLAN while achieving precise synchronization across the entire multi-VLAN network.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements dynamic VLAN-aware processing where boundary clocks automatically adapt their behavior based on the VLAN context of incoming PTP messages. The system dynamically routes and processes synchronization messages according to VLAN identifiers, maintaining measurement precision across different VLANs while keeping the operational complexity manageable through automated adaptation.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3997816B1VLAN-aware clock hierarchy
Publication Date: 2025.08.27 ARISTA NETWORKS INC
  • EP3997816B1 patent drawingFigure 1
  • EP3997816B1 patent drawingFigure 2A
  • EP3997816B1 patent drawingFigure 2B~2C

AI summary

Synchronization of clocks among computing devices in a network includes determining master/slave relations among the computing devices. Some computing devices (e.g., switches) include trunk ports configured to carry traffic for several logical networks; e.g., virtual local area networks, VLANs. A trunk port can be associated with a master / slave setting for each logical network that it is configured for. Synchronization of clocks among the computing devices further includes running a synchronization sequence between a trunk port and each computing device on each of the logical networks configured on the trunk port.