VLC Bitstream Buffering for Fixed-Width Video Output

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Solution Overview

Problem

Current implementations of the H.264 video compression standard, whether in software or hardware, face inefficiencies in processing tasks such as forward and inverse transformations, Hadamard transformations, and quantization, leading to high processor cycle requirements and complexity.

Innovation Solution

A video processor architecture that incorporates hardwired transformation and Hadamard matrices, along with SIMD instructions and quantization lookup tables, to perform these tasks in reduced processor cycles, eliminating the need for frequent memory access and enabling faster data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If video compression is implemented fully in software using general-purpose CPUs, then adaptability and versatility are improved, but processing speed and efficiency deteriorate

Engineering Contradiction:
ImproveadaptabilityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The video processor is divided into specialized functional units including transformation units, Hadamard transformation units, quantization units, and bitstream generation units. Each unit handles specific compression tasks independently, enabling parallel processing while maintaining the adaptability of a software-like architecture through programmable control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate buffers and control logic that mediate between the specialized hardware units and the host system. These intermediaries enable efficient data flow management and allow the processor to operate autonomously, achieving hardware-speed processing while retaining software-level adaptability through programmable control sequences.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If video compression is implemented as specific purpose hardware, then processing speed is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improveprocessing speedVSAvoidhardware complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The video processor is designed as a universal compression engine that can handle multiple video standards and coding modes through programmable control. The same hardware infrastructure supports various transformation types, quantization schemes, and bitstream formats, reducing overall system complexity while maintaining high processing speed through specialized functional units.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The processor utilizes lookup tables for transformation matrices and quantization parameters that can be dynamically loaded and changed without hardware reconfiguration. This allows the system to adapt to different compression standards and modes by simply changing data parameters rather than reconfiguring the hardware architecture, thereby reducing complexity while maintaining speed.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If frequent memory access is used for transformation data, then adaptability is improved, but processor cycle requirements increase

Engineering Contradiction:
ImproveflexibilityVSAvoidprocessor cycles
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The video processor pre-loads transformation matrices, Hadamard matrices, and quantization tables into dedicated on-chip memory structures before processing begins. This preliminary action eliminates the need for frequent external memory accesses during compression operations, significantly reducing processor cycle requirements while maintaining full adaptability through programmable control of the pre-loaded data.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent moves transformation data from external memory space to internal on-chip memory space, effectively changing the dimensional location of data storage. This dimensional shift reduces access latency and eliminates bottlenecks associated with external memory interfaces, allowing the processor to operate at full speed without sacrificing adaptability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7439883B1Bitstream generation for VLC encoded data
Publication Date: 2008.10.21 NVIDIA CORP
  • US7439883B1 patent drawing
  • US7439883B1 patent drawing
  • US7439883B1 patent drawing

AI summary

A bitstream generator is described, for placing variable length coding (VLC) data into a fixed width data stream. The bitstream generator includes an input for receiving VLC data; the VLC data may be separated into a value component, and a length component. The bitstream generator also includes an output buffer, a memory module, for storing the VLC data before sending. The bitstream generator also incorporates a backup buffer, which is used to store any overflow data which does not fit in the output buffer. A comparator is used, to determine how much of the VLC data will fit in the output buffer. Any portion of the VLC data which does not fit in the output buffer is stored in the backup buffer.