VLCT Protocol for Programmable BIST Register Access
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Solution Overview
Problem
Current programmable built-in self test (pBIST) systems for integrated circuits face challenges in programming time and lack the capability to read internal registers, making them inefficient for complex testing and debugging.
Innovation Solution
A programmable built-in self test unit with data registers that allows external access through a two-phase protocol, including a command phase for specifying operations and a data access phase for sequential register access, enabling faster programming and internal register reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If current VLCT programming method is used for pBIST, then programming capability is provided, but programming time is excessively long
Solution Approach 1:
The programming process is divided into two distinct phases: a command phase for setting up test parameters and a data access phase for actual data transfer. This segmentation allows for more efficient processing by separating control operations from data operations, reducing overall programming time.
Solution Approach 2:
Test data and algorithms are pre-loaded into the pBIST unit's data registers during the command phase before actual testing begins. This preliminary action eliminates the need for time-consuming data loading during test execution, significantly reducing programming time.
2Adaptability or versatility
If traditional pBIST architecture is used, then basic testing functionality is provided, but reading internal registers is not supported
Solution Approach 1:
The pBIST unit is designed with universal data registers that can be both written to and read from via the external tester. This multi-functionality allows the same hardware structure to support both traditional programming and new read operations, enhancing versatility without requiring separate read-only memory structures.
Solution Approach 2:
The data registers transition from a traditional static read-only configuration to a dynamic read-write configuration. This dynamic approach allows flexible access modes where registers can be programmed and subsequently read for debugging and verification purposes.
3Ease of operation
If sequential register access is implemented, then reading capability is added, but access time may increase
Solution Approach 1:
The data access phase implements continuous sequential access to multiple data registers without interruption. Once the starting address and count are set in the command phase, the system continuously accesses successive registers in sequence, maximizing throughput and minimizing access time for reading multiple registers.
Data Source
AI summary
An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit receives a command, an address and a data transfer count. The address specifies the initial data register address. The data transfer count corresponds to the amount of data transferred and the number of cycle in the data access phase. The data access phase begins by accessing the data register corresponding to the address from the command phase. During subsequent cycles of the data access phase, the external tester accesses sequential data registers. The programmable built-in self test unit includes a pointer register and an adder to update the address each cycle of the data phase.