Variable Length Decoder Buffer Critical Path Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional variable length decoding (VLD) circuits face challenges in high-compression systems, requiring multiple clock cycles to decode, which exceeds the 7.4-ns clock cycle limit for 135 MHz specifications, leading to a prolonged critical path.
Innovation Solution
A device and method for variable length decoding that incorporates a buffer on the path from the barrel shifter to the coding table, allowing for adjusted critical path timing, utilizing a clock signal to control output and employing additional barrel shifters and multiplexers to manage data selection and shifting, thereby shortening the critical path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional VLD circuit structure is used, then decoding function is achieved, but critical path is prolonged and clock cycle exceeds 7.4-ns limit
Solution Approach 1:
The VLD circuit is divided into multiple independent processing stages: a first VLD circuit processes the first 16-bit data while a second VLD circuit processes the second 16-bit data. This segmentation allows parallel processing of different data segments, reducing the overall critical path length and enabling the system to meet the 7.4-ns clock cycle requirement.
Solution Approach 2:
The patent introduces a time dimension by processing multiple 16-bit data segments in parallel across different clock cycles. The first and second 16-bit data are handled simultaneously in different processing paths, effectively distributing the computational load across time and space dimensions to reduce the critical path duration.
2Productivity
If barrel shifter and VLD table are used for decoding, then variable length decoding is achieved, but decoding time exceeds two clock cycles in high-compression systems
Solution Approach 1:
The barrel shifter is configured to perform preliminary shifting operations on the 32-bit input data to extract the first and second 16-bit data segments before they enter the VLD circuits. This preliminary preparation reduces the processing burden on the decoding stage, enabling faster decoding completion within two clock cycles.
Solution Approach 2:
The patent creates a redundant copy of the VLD processing path by implementing both a first VLD circuit and a second VLD circuit that operate in parallel. This duplication allows simultaneous processing of multiple data segments, effectively doubling the throughput and reducing the average decoding time per segment.
Data Source
AI summary
An device and method for variable length decoding. The device comprises a device for variable length decoding comprising a first register, a second register, a first barrel shifter, a buffer, a coding table and an adding device. The method is characterized in that the buffer is installed on the output path from the barrel shifter to the coding table so as to shorten the critical path.