VLD Doping Structure for Avalanche Current Distribution
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Solution Overview
Problem
Semiconductor devices face a trade-off between reducing ON resistance and maintaining high breakdown voltage, leading to issues with avalanche capacity, where current can easily flow to unintended regions, potentially causing breakdown due to concentrated currents during avalanche operations.
Innovation Solution
A semiconductor device with a VLD (Variation Lateral Doping) structure in the gate pad region, featuring a gentler impurity concentration gradation compared to the base layers, which helps distribute current more evenly and prevent concentration, thereby enhancing avalanche capacity without lowering breakdown voltage or increasing ON resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the wafer specification is made low resistance to reduce ON resistance, then the ON resistance is reduced, but the breakdown voltage is lowered
Solution Approach 1:
The patent applies different impurity concentration profiles to different regions: the cell region uses a standard profile for low ON resistance, while the intermediate region under the gate pad uses a VLD structure with gentler gradation to maintain high breakdown voltage and prevent avalanche current concentration. This local differentiation resolves the trade-off by optimizing each region for its specific function.
Solution Approach 2:
The patent changes the impurity concentration gradient parameter in the intermediate region by introducing a VLD structure with gentler gradation compared to the cell region. This parameter modification allows the intermediate region to withstand higher voltages during avalanche operation while the cell region maintains low resistance for efficient conduction.
2Reliability
If the breakdown voltage is improved by optimization of cell design, then the breakdown voltage is increased, but the current easily flows to portions other than cells causing concentration in avalanche operation
Solution Approach 1:
The patent introduces an intermediate region with a P-type base layer featuring VLD structure between the cell region and gate pad. This intermediate region acts as a mediator that prevents direct current flow from the cell region to the gate pad during avalanche operation, distributing the current more evenly and preventing concentration that would damage the P-type base layer.
Solution Approach 2:
The VLD structure in the intermediate region is designed in advance to cushion against avalanche current concentration. The gentler impurity gradation creates a more gradual electric field distribution that prevents sudden current concentration, protecting the P-type base layer from breakdown during high-stress avalanche operations.
3Reliability
If the P-type base layer under gate pad is formed deeper or made floating to prevent current flow, then the avalanche capacity is improved, but the structure complexity increases
Solution Approach 1:
Instead of changing the structural configuration (depth or floating status), the patent achieves improved avalanche capacity by changing the impurity concentration gradient parameter. The VLD structure with gentler gradation in the intermediate region provides the necessary current distribution benefits while maintaining a simpler, more manufacturable structure compared to deeper or floating base layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The VLD structure effectively improves avalanche capacity by reducing current concentration to the source contact portion, maintaining high breakdown voltage and low ON resistance, thus enhancing the semiconductor device's reliability and performance during switching operations.
Implementation Method 1
an impurity concentration gradation in the gate pad side of the second base layer has a VLD (Variation Lateral Doping) structure which is gentler than an impurity concentration gradation in the first base layer
Data Source
AI summary
A semiconductor device including a semiconductor layer of a first conductivity type in a cell region, a first base layer of a second conductivity type on the semiconductor layer in the cell region; a second base layer of the second conductivity type on the semiconductor layer in an intermediate region; a conductive region of a first conductivity type in the first base layer; a gate electrode on a channel region placed between the conductive region and the semiconductor layer; a first electrode connected to the first and second base layers; a second electrode connected to the semiconductor layer; and a gate pad on the semiconductor layer via an insulating film in a pad region and connected to the gate electrode, an impurity concentration gradation in the gate pad side of the second base layer has a gentler VLD structure than an impurity concentration gradation in the first base layer.