VLIW Processor Instruction Cache Bank Allocation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing VLIW processors face challenges in efficiently executing multiple instruction streams due to the high hardware requirements and limited bandwidth utilization, making it difficult to achieve performance improvements in low-cost systems or embedded image processing.
Innovation Solution
A processor configuration that sets instruction priority orders for multiple instruction streams and designates memory banks based on bank number information, allowing concurrent execution with a minimal hardware setup by optimizing memory bank usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If M instruction caches are provided to concurrently execute M instruction streams, then the number of concurrently executable instructions increases, but hardware cost increases significantly
Solution Approach 1:
The patent merges M instruction caches into a single shared instruction cache that stores instructions for all M instruction streams. The cache is organized with M sets, each set containing L memory banks. This consolidation reduces hardware cost while maintaining the capability to concurrently fetch instructions for multiple instruction streams through intelligent address mapping and bank selection.
Solution Approach 2:
The single instruction cache is designed to serve multiple instruction streams simultaneously by implementing a universal storage structure. The cache can store instructions from different instruction streams in different sets and banks, and the address selector can direct fetches to appropriate locations within the same cache structure, making the cache multi-functional for supporting M instruction streams.
2Device complexity
If instructions are fetched from a single instruction cache for multiple instruction streams, then hardware cost is reduced, but bandwidth utilization becomes limited
Solution Approach 1:
The instruction cache is segmented into M sets, with each set containing L memory banks. This segmentation allows different instruction streams to be directed to different sets and banks, enabling parallel access patterns. The address selector can simultaneously activate multiple banks within the same cache structure, increasing bandwidth utilization while keeping hardware costs low.
Solution Approach 2:
The patent introduces a new dimension for organizing instruction storage by creating a two-dimensional structure with M sets and L banks per set. This dimensional organization allows the system to exploit both set-associative and bank-parallel access patterns, effectively increasing bandwidth utilization without requiring M separate caches.
3Adaptability or versatility
If M program counters and M instruction caches are provided, then concurrent execution of M instruction streams is enabled, but the processor requires a large amount of hardware
Solution Approach 1:
The patent merges M separate instruction cache structures into a single shared cache with M sets. Instead of providing M independent caches, the system uses one cache that can store and serve instructions for all M instruction streams through intelligent addressing and bank selection, significantly reducing hardware requirements while maintaining concurrent execution capability.
Solution Approach 2:
The address selector acts as an intermediary between M program counters and the single instruction cache. It receives address requests from multiple program counters, determines the appropriate set and bank within the cache, and directs the fetch operation accordingly. This intermediary enables multiple instruction streams to share the single cache efficiently.
Data Source
AI summary
A VLIW processor executes a very long instruction word containing a plurality of instructions, and executes a plurality of instruction streams at low cost. A processor executing a very long instruction word containing a plurality of instructions fetches concurrently the very long instruction words of up to M instruction streams, from N instruction caches including a plurality of memory banks to store the very long instruction words of the M instruction streams. The processor may set instruction priority order for each of the instruction streams, designate a memory bank to be used by each of the instruction streams from the memory banks based on bank number information, which indicates a number of memory banks each instruction stream uses, and an instruction address of each of the instruction streams, determine a memory bank to be used in descending priority order based on the instruction stream priority order when a plurality of instruction streams are to use a same memory bank, and supply an instruction address of a corresponding instruction stream to the determined memory bank.