Dynamic Clock Gating for VLIW Cluster Power Reduction
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Solution Overview
Problem
Existing clustered VLIW processors and runtime reconfigurable architectures face limitations in power dissipation and processing speed due to inter-cluster bus overhead and poor programming abstraction, which restricts their ability to efficiently execute programs with varying instruction level parallelism.
Innovation Solution
A clustered VLIW processing system with a runtime reconfigurable inter-cluster interconnect allows dynamic allocation of computing resources, enabling efficient execution of high ILP kernels while reducing power dissipation by idling clusters during low ILP segments, and providing a scalable abstraction similar to general-purpose processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clustered VLIW architecture is used to accelerate high ILP code, then processing speed is improved, but power dissipation increases due to inter-cluster bus overhead and unused clusters
Solution Approach 1:
The patent implements dynamic clock gating that adjusts the clock frequency of individual clusters based on their activity level. When a cluster is idle or handling low-ILP code, its clock is gated or slowed down, reducing dynamic power consumption proportionally. This allows the system to maintain high processing speed for active clusters while minimizing power dissipation for inactive or low-utilization clusters.
Solution Approach 2:
The system changes the operational parameters (clock frequency) of clusters dynamically based on workload characteristics. By monitoring instruction level parallelism and cluster utilization, the system adjusts clock rates to optimize the trade-off between processing speed and power dissipation, allowing clusters to operate at minimal necessary frequency rather than always at maximum speed.
2Productivity
If the number of clusters is increased to handle high ILP code, then processing capability is improved, but device complexity and inter-cluster bus overhead increase
Solution Approach 1:
The patent segments the inter-cluster communication into hierarchical levels: fast on-chip interconnect for immediate neighbor communication and slower off-chip memory access for distant data. This segmentation allows more clusters to be added to the system without proportionally increasing the complexity of the inter-cluster bus, as clusters can efficiently communicate with local neighbors while accepting that distant communication will be slower.
3Productivity
If static scheduling is used in VLIW architecture, then instruction level parallelism is improved, but program size overhead increases due to send/receive instructions
Solution Approach 1:
The patent extracts and eliminates the need for explicit send/receive instructions by implementing a compiler that automatically schedules instructions across clusters and manages data movement. The compiler generates optimized VLIW instructions that implicitly handle inter-cluster data transfer, removing the overhead of explicit communication instructions from the program while maintaining high instruction level parallelism.
4Adaptability or versatility
If runtime reconfiguration is implemented in coprocessor, then adaptability is improved, but reconfiguration time and resource overhead increase
Solution Approach 1:
The patent performs reconfiguration preparation in advance by having the compiler generate cluster configuration information during compilation. The coprocessor receives pre-configured instruction streams that include cluster assignment and interconnect topology information, allowing the hardware to be reconfigured for the upcoming workload without runtime reconfiguration overhead. This preliminary action eliminates reconfiguration time during actual execution.
Data Source
AI summary
Clustered VLIW processing elements, each preferably simple and identical, are coupled by a runtime reconfigurable inter-cluster interconnect to form a coprocessor executing only those portions of a program having high instruction level parallelism. The initial portion of each program segment executed by the coprocessor reconfigures the interconnect, if necessary, or is skipped. Clusters may be directly connected to a subset of neighboring clusters, or indirectly connected to any other cluster, a hierarchy exposed to the programming model and enabling a larger number of clusters to be employed. The coprocessor is idled during remaining portions of the program to reduce power dissipation.