VLIW Conditional Execution Slots in Fixed-Length Execute Packets
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In VLIW processors, conditional instruction execution techniques face challenges due to the need for additional bits to specify multiple registers, which reduces opcode space and can exceed instruction length, especially when multiple functional units operate in parallel.
Innovation Solution
The solution involves employing two conditional execution auxiliary instructions for disparate subsets of functional units and dividing functional units into scalar and vector sets with separate register files, limiting simultaneous access and optimizing register usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple registers are made available to control conditional execution, then conditional execution capability is improved, but the number of bits needed in each instruction increases, reducing opcode space
Solution Approach 1:
The patent divides the functional units into two separate sets (first set and second set), each with its own conditional execution auxiliary instruction. This segmentation allows the processor to handle conditional execution for different functional unit subsets independently, reducing the bits needed in each instruction while maintaining comprehensive conditional execution capability across all functional units.
2Adaptability or versatility
If conditional execution bits are added to every instruction, then conditional execution is enabled, but instruction length increases beyond fixed length constraints
Solution Approach 1:
The patent extracts the conditional execution control mechanism from individual operational instructions and creates separate auxiliary instructions. These auxiliary instructions contain the conditional execution bits and are executed independently before the operational instructions, allowing operational instructions to maintain their fixed length while still supporting conditional execution through the separate auxiliary instruction mechanism.
3Ease of manufacture
If fixed instruction length is maintained, then coding/decoding simplicity is preserved, but the ability to specify multiple registers for conditional execution is limited
Solution Approach 1:
The patent introduces auxiliary instructions as intermediary elements between the instruction stream and the operational instructions. These auxiliary instructions serve as mediators that carry the conditional execution register specification information, allowing the main operational instructions to maintain their simple fixed-length format while the auxiliary instructions handle the complex register specification for conditional execution control.
Data Source
AI summary
In an example, a device includes a register file; a set of functional units coupled to the register file; and an instruction decoder coupled to the register file and to the set of functional units. The instruction decoder receives an executable instruction directed to a specific functional unit of the set of functional unit. The executable instruction includes a segment specifying a register of the register file. The instruction decoder also provides the executable instruction to the specific functional unit. The specific functional unit then determines whether to execute the executable instruction based on a value stored in the register of the register file specified by the segment of the executable instruction.