VLIW DSP Architecture Scalability via Modular Datapath Clusters
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Solution Overview
Problem
Current digital signal processors (DSPs) face challenges in scalability, customizability, and programmability, limiting their ability to efficiently handle diverse applications and exploit reduced semiconductor feature geometries for performance gains.
Innovation Solution
A scalable and customizable enhanced VLIW DSP platform is created using a VLIW template, reconfigurable compiler, and simulator, allowing for rapid evaluation of architecture alternatives, with customizable datapath clusters and specialized functional units, enabling targeted DSP design and rapid prototyping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data path replication is used to scale computational capacity, then parallelism is improved, but device complexity increases
Solution Approach 1:
The processor is divided into multiple identical or semi-identical data paths (e.g., 2, 4, or 8 datapaths), each capable of independent operation. This segmentation allows computational capacity to scale by simply replicating functional units while maintaining manageable complexity through modular design and standardized interfaces.
2Productivity
If more functional units are added to increase computational capacity, then productivity is improved, but ease of operation deteriorates
Solution Approach 1:
The processor employs a unified instruction set architecture and common control logic that can operate across different numbers of data paths (2, 4, or 8). This universality allows the same software to run on various configurations without modification, maintaining ease of operation while enabling high productivity through parallel execution.
3Productivity
If instruction level parallelism is increased to exploit reduced semiconductor geometries, then productivity is improved, but device complexity increases
Solution Approach 1:
The compiler performs preliminary analysis and scheduling of instructions to identify and exploit parallelism opportunities before code generation. By pre-organizing instruction sequences to maximize parallel execution across multiple data paths, the system achieves high productivity without requiring complex runtime control logic, as much of the parallelism management is resolved at compile time.
Data Source
AI summary
A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters, reconfiguring a compiler for the selected architecture parameters, compiling the benchmark, reconfiguring a data processor simulator to the selected architecture parameters, running the complied benchmark on the reconfigured simulator, automatically synthesizing an integrated circuit physical layout and evaluating performance of the selected architecture parameters against predetermined criteria. The method varies the selected architecture parameters upon failure to meet criteria until evaluation of the selected architecture parameters meets the criteria. The method selects a number of datapath clusters to avoid too many input/output ports in data registers.