VLIW Graphics Pipeline Gatekeeper for Power Reduction

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Solution Overview

Problem

Conventional three-dimensional graphics processors require significant processing and memory resources, and consume substantial power, making them unsuitable for resource-constrained devices such as portable game consoles and wireless communication devices, where size and power efficiency are critical.

Innovation Solution

A graphics pipeline architecture that includes a setup stage, raster stage, gatekeeper stage, program sequencer, arithmetic logic unit stage, and data write stage, utilizing a very long instruction word (VLIW) machine and scoreboarding techniques to optimize processing and reduce power consumption by limiting unnecessary calculations and discarding non-contributory pixels early in the pipeline.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional multi-pass processing stages are used, then processing capability is improved, but power consumption increases significantly

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The processing pipeline is divided into multiple sequential stages (setup stage, raster stage, gatekeeper stage, program sequencer, ALU stage, data write stage), where each stage performs a specific function. This segmentation allows early discarding of non-contributory pixels before they consume power in subsequent stages, thus maintaining processing capability while reducing overall power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gatekeeper stage performs preliminary filtering of pixels before they reach the ALU stage. By identifying and discarding non-contributory pixels (those that will not affect the final image) in advance, the system prevents wasted power consumption in subsequent processing stages while maintaining the necessary processing capability for visible pixels.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If extensive processing stages are implemented, then image rendering quality is improved, but device size increases

Engineering Contradiction:
Improveimage rendering qualityVSAvoiddevice size
Core Design Contradiction:
Manufacturing precisionVSVolume of moving object

Solution Approach 1:

The invention extracts and removes non-contributory pixels from the processing stream at the gatekeeper stage, before they can consume resources in subsequent processing stages. This extraction of unnecessary processing elements maintains image rendering quality for visible pixels while reducing the overall computational burden and device resource requirements.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

By performing preliminary identification and discarding of non-contributory pixels in the gatekeeper stage, the system prepares the data stream in advance to eliminate wasted processing. This preliminary action ensures that only necessary pixels proceed through the full processing pipeline, maintaining rendering quality while reducing device complexity and size.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If all pixels are processed through the pipeline, then complete image rendering is achieved, but processing time is increased

Engineering Contradiction:
Improveimage rendering completenessVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The gatekeeper stage performs preliminary filtering to identify and discard non-contributory pixels before they enter the time-consuming ALU processing stage. This preliminary action ensures that only pixels that will actually contribute to the final image undergo full processing, thereby maintaining complete image rendering quality while significantly reducing overall processing time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The processing pipeline is segmented into distinct stages with the gatekeeper stage performing early filtering. This segmentation allows the system to quickly eliminate non-contributory pixels in a low-cost stage before committing resources to time-intensive processing in later stages, thus reducing total processing time while maintaining rendering completeness.

Inventive Principle:
Principle #1Segmentation

4Illumination intensity

If resource-constrained devices use traditional graphics processing, then display capability is limited, but power supply drain increases

Engineering Contradiction:
Improvedisplay capabilityVSAvoidpower supply drain
Core Design Contradiction:
Illumination intensityVSUse of energy by moving object

Solution Approach 1:

The gatekeeper stage performs preliminary discarding of non-contributory pixels before they consume power in subsequent processing stages. This preliminary filtering reduces the overall power consumption of the graphics processing system, enabling resource-constrained devices to maintain acceptable display capability while extending battery life and reducing power supply drain.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

By segmenting the processing pipeline and adding the gatekeeper stage, the system enables early elimination of unnecessary pixel processing. This segmentation allows power-constrained devices to maintain display capability for visible pixels while dramatically reducing the power consumption associated with processing non-contributory pixels that would otherwise waste energy resources.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8775777B2Techniques for sourcing immediate values from a VLIW
Publication Date: 2014.07.08 NVIDIA CORP
  • US8775777B2 patent drawing
  • US8775777B2 patent drawing
  • US8775777B2 patent drawing

AI summary

Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded by utilizing a block of a very long instruction word, which is normally utilized by the first arithmetic logic unit component, for the second arithmetic logic unit component if the sub-instruction expansion condition exists.