VLIW Processor Instruction Code Compression
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Solution Overview
Problem
In VLIW processors, the increasing program code size leads to higher cache miss rates due to increased instruction fetching, degrading processor performance, particularly in embedded systems where instruction level parallelism is utilized for operations like FFT and digital filtering.
Innovation Solution
An electronic device and method that generate a new VLIW instruction by identifying and combining slots with the same opcode in a VLIW processor, reducing redundancy and optimizing instruction code size by using a single opcode occurrence along with register index fields and state bits, thereby reducing program memory size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If program code size increases to support more instructions, then instruction functionality is improved, but cache miss rate increases and processor performance degrades
Solution Approach 1:
The patent merges multiple instruction slots with the same opcode into a single compressed instruction representation. Instead of storing each slot separately with its full opcode, the invention combines them using a single opcode field with associated register index fields and state bits, reducing program code size and improving cache utilization while maintaining the ability to execute multiple operations.
Solution Approach 2:
The patent changes the parameter representation by introducing state bits that indicate which slots share the same opcode. This allows the processor to dynamically interpret the compressed instruction format, expanding a single stored instruction into multiple execution slots based on the state bits, thereby reducing code size without losing functional capability.
2Quantity of substance
If program code size increases, then more instructions can be stored, but the number of instruction fetches increases and cache miss rate increases
Solution Approach 1:
The patent combines multiple instruction slots into a single compressed representation in program memory. By merging slots with identical opcodes into one stored instruction with state bits indicating slot sharing, the total number of instruction fetches is reduced, decreasing cache miss rates and improving execution efficiency.
3Quantity of substance
If redundancy of the same opcode is eliminated, then program memory size is reduced, but instruction encoding complexity increases
Solution Approach 1:
The patent segments the instruction encoding into distinct fields: opcode field, register index fields, and state bits. This segmentation allows the compiler to systematically identify slots with the same opcode and apply compression rules, managing encoding complexity through structured field division while achieving significant program memory size reduction.
Solution Approach 2:
The patent introduces state bits as a new parameter that encodes information about opcode sharing across slots. This additional parameter enables the representation of multiple slots with a single opcode, reducing redundancy in program memory while the systematic use of state bits manages the complexity of the encoding process.
Data Source
AI summary
An electronic device including a memory; and a processor configured to generate an instruction code based on a same opcode when the same opcode is used in one or more slots defined in the memory upon application compiling.