VLIW Instruction Compression via Index Code and NOP Removal
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Solution Overview
Problem
Current instruction word compression methods for VLIW computers require additional storage space and complex circuit logic, and are not optimal for parallel processing due to the need for complex allocation logic and interconnect networks.
Innovation Solution
An instruction word compression apparatus and method that generates an index code for NOP instruction words, deletes these words, and converts effective instruction words to include the index code, reducing storage space without additional circuit logic and optimizing performance for parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If NOP instruction words are allocated to functional units not being operated at each execution time, then parallel processing capability is maintained, but storage space requirement is increased
Solution Approach 1:
The patent extracts and removes NOP instruction words from the instruction stream, retaining only effective instruction words. This is achieved by generating an index code that identifies NOP words and selectively deleting them, thereby reducing storage space while preserving the parallel processing capability through the retained effective instructions.
Solution Approach 2:
The patent changes the parameter of instruction word format by introducing an index code field to effective instruction words. This index code indicates the number of NOP words that were removed, allowing the system to maintain parallel processing information while using less storage space for the instruction words themselves.
2Quantity of substance
If end code and parallel bit are used for instruction compression, then storage space is reduced, but device complexity is increased
Solution Approach 1:
The patent merges the compression function with the existing instruction word format by integrating the index code into the effective instruction words themselves. This eliminates the need for separate end codes and parallel bits, reducing device complexity while maintaining storage space reduction benefits.
Solution Approach 2:
The index code serves multiple functions: it indicates the number of removed NOP words, enables compression, and maintains parallel processing information. This multi-functionality eliminates the need for separate dedicated compression fields, thereby reducing overall device complexity.
Data Source
AI summary
An apparatus and a method are provided for a parallel processing very long instruction word (VLIW) computer. The apparatus includes: an index code generation unit sequentially generating an index code, which is associated with a number of no operation (NOP) instruction word between effective instruction words, with respect to each of instruction word groups to be executed in a VLIW computer; an instruction compression unit sequentially deleting the NOP instruction word which corresponds to the index code with respect to each of instruction word groups; and an instruction word conversion unit converting the effective instruction words to include the index code, the effective instruction words corresponding to the NOP instruction words.