VLIW Instruction Set Generation for Memory Compaction
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Solution Overview
Problem
Very long instruction word (VLIW) data processors face high program memory storage requirements due to inefficient use of instruction length, leading to overhead in data storage when not all operations are performed in parallel.
Innovation Solution
The method involves grouping instructions that communicate control signals to the same command buses, forming instruction sets with fewer bits, reallocating excess bits to identification bits, and optimizing instruction field widths to reduce program memory storage needs while maintaining decoder complexity control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If VLIW processors use fixed-length long instructions to support parallel operations, then instruction level parallelism capability is improved, but program memory storage requirements increase
Solution Approach 1:
The patent segments the instruction stream into clusters of instructions that share the same command bus configuration. Each cluster is represented by a compact instruction set that identifies the cluster type and the specific command buses to be activated. This segmentation allows the processor to use shorter encoded instructions while maintaining the ability to support multiple parallel operations through cluster-based organization.
Solution Approach 2:
The patent introduces a new dimension to instruction encoding by using cluster identification fields instead of directly encoding all possible command bus configurations in each instruction. The compact instruction sets use identification bits to reference pre-defined clusters, effectively moving from a flat encoding approach to a hierarchical one that reduces the number of bits needed per instruction while preserving parallelism capabilities.
2Productivity
If VLIW processors encode multiple independent operations in each instruction, then execution efficiency is improved, but instruction width increases
Solution Approach 1:
The patent applies partial action by activating only the specific command buses needed for each instruction cluster rather than encoding all possible operations in every instruction. The compact instruction sets specify only the relevant subset of command buses to be activated, reducing instruction width while maintaining execution efficiency for the required operations.
3Quantity of substance
If instruction formats are narrowed to reduce code size, then program memory storage is reduced, but the number of identifiable instruction sets decreases
Solution Approach 1:
The patent merges multiple individual instruction representations into unified compact instruction sets that represent clusters of instructions with similar command bus configurations. By combining the functionality of multiple full-width instructions into shorter clustered representations, the system reduces code size while maintaining the ability to identify and execute diverse instruction types through the cluster identification mechanism.
Data Source
AI summary
A method of generating at least one instruction set from a plurality of program instructions, said plurality of program instructions comprising a plurality of instruction fields each of said instruction fields operable on decoding to generate control signals for transmission by individual command buses, said method comprising the steps of: determining which combination of command buses each instruction is operable to communicate control signals to and forming a cluster of instructions from instructions that communicate control signals to a same combination of command buses; developing at least one instruction set for at least some of said instruction clusters, said at least one instruction set having fewer bits than said program instruction; specifying a number of identification bits within said at least one instruction set operable to identify said instruction set; determining a number of bits required for each instruction field within said at least one instruction set to specify all possible control signals that can be sent by said at least one instruction set along a respective one of said command buses and reallocating any bits that are allocated to said instruction field that are in excess of said determined required number to said identification bits, such that an increased number of different instruction sets can be identified by said identification bits.