Loop Scheduling for VLIW Processors Using Priority-Based Resource Allocation

The patent segments the scheduling process into distinct priority levels (higher priority loops and lower priority loops). The scheduler first allocates execution units to higher priority loops, then assigns remaining units to lower priority loops. This segmentation simplifies the overall scheduling complexity by breaking it into manageable hierarchical stages while maintaining high instruction-level parallelism through concurrent loop execution.

The patent applies preliminary action by first scheduling higher priority loops and determining their execution unit requirements before allocating resources to lower priority loops. The scheduler performs preliminary allocation to critical loops, then utilizes remaining execution units and idle cycles for lower priority loops. This approach ensures that higher priority loops receive guaranteed resources for accurate execution while lower priority loops utilize leftover resources, minimizing their time loss without compromising overall system reliability.

The patent implements continuity of useful action by continuously utilizing available execution units across different priority levels. Instead of leaving execution units idle during higher priority loop execution, the scheduler continuously assigns lower priority loop instructions to available units. This continuous utilization reduces total execution cycles and improves productivity while distributing energy consumption more efficiently across the processing timeline, preventing energy waste from idle hardware resources.