VLIW Pixel Average Sub-Instruction Parallel Processing
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Solution Overview
Problem
Conventional systems are inefficient in performing pixel averaging, particularly in video processing, as they typically calculate pixel averages sequentially, which is time-consuming and requires recalculation for large images with fast frame display rates.
Innovation Solution
A novel computer processor chip with a sub-instruction for parallel pixel averaging, utilizing a scalable VLIW processing core and pixel average sub-instruction that allows multiple pixel averages to be performed in a single instruction issue, enabling simultaneous processing of multiple pixel pairs and accommodating different rounding methodologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sequential pixel averaging is used, then implementation simplicity is maintained, but processing speed and efficiency deteriorate
Solution Approach 1:
The patent segments the pixel averaging operation into multiple parallel execution paths within a single instruction cycle. The VLIW architecture divides the processing into separate functional units that can simultaneously compute averages for different pixel pairs, effectively segmenting the sequential operation into parallel components without requiring complex external hardware additions
Solution Approach 2:
The patent transitions from sequential single-instruction processing to parallel multi-operation processing by utilizing the VLIW instruction format. This dimensional change in instruction processing allows multiple pixel averaging operations to be issued and executed in parallel within a single clock cycle, fundamentally changing the time dimension of operation execution
2Productivity
If multiple pixel averages are performed sequentially, then computational accuracy is maintained, but processing time increases
Solution Approach 1:
The patent performs preliminary preparation by organizing pixel data into parallel-access structures and pre-configuring the VLIW instruction streams. This allows multiple pixel averaging operations to be initiated simultaneously without sequential delays, as the data and instructions are prepared in advance for parallel execution
Solution Approach 2:
The patent ensures continuous processing by utilizing all functional units throughout each clock cycle. The VLIW architecture allows multiple pixel averaging operations to proceed simultaneously without idle cycles, maintaining continuous useful action across all processing units and eliminating gaps between operations
3Adaptability or versatility
If conventional add-shift algorithm is used for pixel averaging, then implementation simplicity is maintained, but processing capacity is limited to two pixels at a time
Solution Approach 1:
The patent creates a universal pixel averaging unit that can handle multiple pixel pairs simultaneously through the VLIW architecture. The same basic add-shift algorithm is replicated across multiple functional units, each capable of independent operation, allowing the system to process multiple pixel averages in parallel while maintaining the simplicity of the original algorithm
Data Source
AI summary
According to the invention, a process for averaging two pixel values is disclosed. In one step, an instruction is decoded. A plurality of first operands is loaded from a first input register. A plurality of second operands is loaded from a second input register. An average of one of the plurality of first operands and one of the plurality of second operands is produced. The average is stored in an output register.