VLIW Processor Compact Instruction Format
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Solution Overview
Problem
Conventional VLIW processors face a challenge with large circuit size due to the extensive number of bits required for register specification in very long instruction words, leading to increased complexity and power consumption.
Innovation Solution
A VLIW processor design that includes a register specifying field and register allocation information to standardize operand specification, allowing for a compact instruction format with reduced register specification bits, and utilizing temporary registers to optimize instruction execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If each instruction field has separate register specifying areas (src1, src2, dst) to enable parallel execution of multiple instructions, then the processing speed is improved, but the total number of bits for register specification becomes very large
Solution Approach 1:
The patent merges the register specifying areas of multiple instruction fields into a shared register file structure. Instead of having separate src1, src2, dst areas for each instruction field, the invention combines these into a unified register specification mechanism that serves multiple instruction fields simultaneously, thereby reducing the total bit count while maintaining parallel execution capability
Solution Approach 2:
The patent creates a universal register specification mechanism that can be used by multiple instruction fields. The shared register file and unified specifying areas serve multiple purposes across different instruction fields, allowing the same hardware structure to support parallel execution of multiple instructions without requiring dedicated register specification resources for each field
2Productivity
If the number of registers simultaneously connected to input ports of operation units is increased to support more instructions, then the parallel processing capability is improved, but the number of output ports required from the register file increases, leading to larger circuit size
Solution Approach 1:
The patent merges multiple register connections into a shared register file structure with unified input and output ports. By combining the register specification paths and sharing the register file resources across multiple instruction fields, the invention reduces the total number of required ports while maintaining the ability to support parallel execution of multiple instructions
Data Source
AI summary
A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.