VLIW Processor Parallel Comparison Logic for Conditional Judgment
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Solution Overview
Problem
Existing VLIW processors face inefficiencies in executing complex conditional judgment processing due to high branch instruction execution times and excessive hardware size, particularly in image processing applications like edge detection, where existing techniques either limit efficiency gains or require large circuit sizes.
Innovation Solution
A VLIW processor architecture with multiple comparison operation units and synthesis designation fields allows for efficient execution of complex conditional judgments by performing parallel comparisons and logical operations within a single cycle, reducing circuit size and improving processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If branch instructions are used for complex conditional judgment processing, then the processing can be implemented in existing VLIW processors, but the execution time increases significantly due to branch penalties
Solution Approach 1:
The patent segments the conditional judgment processing into multiple parallel comparison operations within a single VLIW instruction. Instead of using sequential branch instructions, the invention divides the complex condition into multiple simple comparison operations that can be executed simultaneously in parallel, eliminating branch penalties and significantly reducing execution time.
Solution Approach 2:
The patent transitions from sequential time-based execution (branch instructions executed one after another) to spatial parallel execution (multiple comparisons executed simultaneously). By utilizing the parallel processing capability of VLIW architecture, the invention executes multiple comparison operations in the same clock cycle, effectively moving from a time-dimensional approach to a space-dimensional approach.
2Productivity
If predicate registers are used to eliminate conditional branching, then the number of register file transfers is reduced, but the effectiveness is limited for complex hierarchical conditional structures
Solution Approach 1:
The patent creates a universal processing mechanism that handles both simple and complex hierarchical conditional structures through the same parallel comparison approach. The synthesized comparison result operation unit can process various types of conditional judgments uniformly, making the system adaptable to different complexity levels without requiring different architectural approaches.
Solution Approach 2:
The patent merges multiple comparison operations and their results into a single synthesized comparison result through logical operations. By combining multiple comparison outcomes using AND/OR operations within the same instruction cycle, the invention efficiently handles complex hierarchical conditions while maintaining the benefits of reduced register transfers.
3Loss of time
If sum-of-products circuits are provided in parallel for complex conditional judgment, then conditional branching can be achieved in one cycle, but the hardware size increases excessively
Solution Approach 1:
The patent employs dynamic instruction formatting where the VLIW instruction structure adapts to the complexity of the conditional judgment. Rather than providing fixed parallel sum-of-products circuits for all possible conditions, the system dynamically configures the number and type of comparison operations based on the actual conditional structure, optimizing the balance between speed and hardware usage.
Solution Approach 2:
The patent changes the parameters of the comparison operations by allowing flexible configuration of comparison types (equal, not equal, greater than, less than, etc.) and logical operations (AND, OR). This parameter flexibility enables the system to handle complex conditions using a manageable number of standardized comparison units rather than requiring dedicated circuits for each possible condition.
4Speed
If multiple comparison operations are executed in parallel within a single VLIW instruction, then processing speed increases, but the instruction structure becomes more complex
Solution Approach 1:
The patent introduces an intermediary synthesized comparison result operation unit that mediates between multiple parallel comparison operations and the final result. This intermediary component consolidates the outputs of multiple comparisons through logical operations, providing a clean interface that simplifies the overall instruction structure while enabling parallel execution of multiple comparisons.
Data Source
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AI summary
A first operation unit 130 outputs, as a first operation result CR1, an output of a first comparison operation unit 122, or an AND or OR of the output and a value already held in a register 50 according to a first control signal ctrl. A second operation unit 140 outputs, as a second operation result CR2, an output of a second comparison operation unit 124, or an AND or OR of the output and a value already held in the register 50 according to a second control signal ctr2. A third operation unit 150 outputs, as an execution result, the first operation result CR1, or an AND or OR of the first operation result CR1 and the second operation result CR2 to the register 50 according to a third control signal ctr3. The register 50 newly holds and outputs the execution result from the third operation unit 150.