VLIW Processor Special Header Expands Instruction Set Space
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Solution Overview
Problem
Existing programmable data processors face limitations in opcode space and 'code bloat' due to fixed instruction word lengths, making it difficult to implement additional data processing functions without significant changes or mode switching overhead.
Innovation Solution
A very long instruction word data processor uses a special header to decode instructions differently, allowing for extended opcode bits and variable instruction lengths within a fetch packet, enabling the inclusion of both normal and reduced-length instructions without mode switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the instruction word length is fixed at 32 bits, then the processor can maintain consistent decoding logic, but the opcode space becomes limited and cannot accommodate additional data processing functions
Solution Approach 1:
The instruction word is segmented into different functional parts: a header portion that identifies special instructions, and a body portion that contains the actual operation codes. This segmentation allows the header to carry extension information while the body maintains compatibility with existing decoding logic, effectively expanding opcode space without increasing overall instruction word length.
Solution Approach 2:
A header structure is introduced as an intermediary element between the instruction fetch mechanism and the decoding logic. The header contains extension opcode bits that mediate between the limited 32-bit instruction word and the need for expanded opcode space, allowing additional data processing functions to be defined without changing the fundamental instruction word length.
2Adaptability or versatility
If mode switching is implemented to access extended instructions, then additional data processing functions can be accessed, but significant overhead is introduced in tracking and changing modes
Solution Approach 1:
The header structure is prepared in advance within the instruction stream itself, containing all necessary extension opcode bits and decoding information. This preliminary action eliminates the need for runtime mode switching, as the decoding mode is predetermined and embedded in the instruction header, allowing immediate execution without tracking or changing processor modes.
Solution Approach 2:
The mode switching overhead is extracted and eliminated by embedding the decoding mode information directly in the instruction header rather than relying on separate mode registers or state machines. This extraction of mode information into the instruction stream itself allows extended instructions to be accessed without introducing mode switching overhead.
3Quantity of substance
If variable length instructions are used, then code size is reduced and memory requirements decrease, but distinguishing between different instruction lengths becomes complex
Solution Approach 1:
Different parts of the instruction stream are assigned different qualities: headers have a unique encoding pattern that locally identifies them, while instruction bodies maintain standard formatting. This local quality differentiation allows the decoder to easily distinguish between headers and regular instructions based on the header's unique encoding, simplifying variable length instruction handling.
Solution Approach 2:
The header uses a unique encoding pattern that acts as a visual marker or 'color change' to distinguish it from regular instructions. This distinctive header encoding allows the decoding logic to immediately identify and handle variable length instructions differently from standard 32-bit instructions, reducing the complexity of instruction differentiation.
4Adaptability or versatility
If a special header with unique encoding is used to enable extended opcodes, then the instruction set can be expanded, but the decode hardware complexity increases
Solution Approach 1:
The decoding process is segmented into two independent stages: header decoding to identify extension opcode bits, and body decoding to execute the actual instruction. This segmentation allows each stage to be optimized independently, reducing overall decode hardware complexity while still enabling extended instruction set space through the header's unique encoding.
Data Source
AI summary
This invention is useful in a very long instruction word data processor that fetches a predetermined plural number of instructions each operation cycle. A predetermined one of these instructions is used as a special header. This special header has a unique encoding different from any normal instruction. When decoded this special header instructs decode hardware to decode this fetch packet in a special way. In one embodiment a bit field in the header signals the decode hardware whether to decode each instruction word normally or in an alternative way. The header may include extension opcode bits corresponding to each of the other instruction slots. In another embodiment another bit field signals whether to decode an instruction field as one normal length instruction or as two half-length instructions.