Buffer Insertion for VLSI Wirelength Reduction
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Solution Overview
Problem
In integrated circuit design, existing buffer insertion methods lead to inefficient wirelength and increased power consumption due to complex wiring and dense logic cell placement, which adversely affect routability and timing requirements.
Innovation Solution
A method involving high fanout clustering of net sinks and rewired buffers is employed, where buffers are inserted at the closest point to the source on each cluster's bounding box, forming a buffer tree to reduce wirelength and optimize routing, using a nearest neighbor algorithm and Voronoi diagrams to construct efficient spanning graphs and clusters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional buffer insertion methods are used to meet timing requirements, then timing objectives are achieved, but wirelength increases and power consumption rises
Solution Approach 1:
The patent divides the net into multiple clusters of sinks, with each cluster served by a dedicated buffer. This segmentation allows the wire routing to be optimized within each cluster rather than spanning the entire net, reducing total wirelength while maintaining timing requirements through distributed buffer placement.
Solution Approach 2:
The patent applies different routing strategies to different regions of the net by creating clusters with local bounding boxes. Each cluster's wire routing is optimized independently based on its local geometry and timing requirements, allowing for more efficient local wirelength optimization while meeting overall timing objectives.
2Reliability
If more buffers are inserted to fix electrical violations and achieve timing objectives, then timing and electrical requirements are met, but device complexity and buffer count increase
Solution Approach 1:
The patent merges multiple sinks into clusters that are served by shared buffers. By combining the service function of multiple buffers into fewer cluster-level buffers, the total buffer count is reduced while still meeting electrical and timing requirements through the clustered architecture.
Solution Approach 2:
Each buffer serves multiple sinks within its cluster, making it a multi-functional element that addresses timing, electrical, and routing requirements for multiple destinations simultaneously. This universal approach reduces the total number of buffers needed compared to dedicated buffers for each sink.
3Area of stationary object
If dense logic cell placement is used to increase integration, then area utilization improves, but wirelength increases and routability deteriorates
Solution Approach 1:
The patent segments the densely placed logic cells into clusters based on net topology and timing requirements. This segmentation creates manageable routing regions that maintain high area utilization while simplifying the routing problem within each cluster, thereby improving overall routability despite dense placement.
Solution Approach 2:
The patent changes the routing parameters by optimizing wire paths within each cluster's bounding box and using hierarchical routing strategies. This allows efficient routing through densely placed cells by adapting routing parameters to the local cluster geometry, maintaining both high area utilization and good routability.
Data Source
AI summary
Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.