VLSI Clock Pathway Power Reduction via Redundant Delay Removal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
VLSI circuits often include unnecessary circuit elements that draw power, leading to increased energy consumption. Specifically, in clock pathways, redundant delay elements consume additional power without contributing to the circuit's performance.
Innovation Solution
A method and system for power reduction in VLSI circuits by identifying and removing redundant delay elements from clock pathways. This involves calculating a timing budget based on circuit design data, identifying delay elements within the delay element chain that can be removed without affecting performance, and updating the circuit design to remove these elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay elements are added to clock pathways to adjust timing, then timing precision is improved, but power consumption increases
Solution Approach 1:
The patent extracts and removes redundant delay elements from the clock pathway that are no longer needed after timing closure. By identifying and eliminating these unnecessary components, the invention reduces power consumption while maintaining the required timing precision through the remaining essential delay elements.
Solution Approach 2:
The invention discards redundant delay elements that were initially added for timing adjustment but are not needed in the final optimized design. The timing precision is recovered and maintained through the essential delay elements that remain after the removal process.
2Reliability
If circuit elements are added to meet timing requirements, then timing budget is satisfied, but device complexity increases
Solution Approach 1:
The patent extracts and removes unnecessary delay elements from the circuit after timing closure has been achieved. This reduces device complexity by eliminating redundant components while maintaining timing budget satisfaction through the essential elements that remain.
Solution Approach 2:
The invention performs timing analysis and identifies redundant elements before finalizing the circuit design. By conducting this preliminary identification and removal process, the timing budget is satisfied with the minimum necessary circuit elements, avoiding unnecessary complexity.
3Reliability
If redundant circuit elements are kept in the design, then design robustness is improved, but power consumption increases
Solution Approach 1:
The patent extracts and removes redundant delay elements that consume power without contributing to design robustness. The essential elements that provide robustness are retained, while unnecessary components are eliminated to reduce power consumption.
Solution Approach 2:
The invention discards redundant circuit elements that were added for robustness but are not needed in the optimized design. The necessary robustness is recovered and maintained through the essential elements that remain after removal.
Data Source
AI summary
Methods, systems, and products for power reduction by removal of redundancy in clock pathways of VLSI circuits includes: calculating, based on a circuit design data file, a timing budget for an LCB (local clock buffer) and an associated group of latches receiving a clock signal from the LCB, where the circuit design data file includes a structural representation of a circuit design and timing data, identifying, based on the timing budget, a delay element to remove, the delay element included within a delay element chain associated with the LCB, and removing the delay element from the circuit design.