VLSI Flop Type Selection to Avoid Min-Time and Race Conditions
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Solution Overview
Problem
Integrated circuit (IC) design faces challenges in determining the optimal type of flop circuits, such as master-slave flip-flops or pulse flops, especially for critical flops, which can lead to costly redesigns and performance sacrifices due to potential race conditions and min-time problems.
Innovation Solution
A method and apparatus that allow flop circuits to operate in two modes: one mode as master-slave flip-flops and another mode as pulse flops, by aligning clock signals to prevent concurrent transparency of master and slave latches, enabling determination of the best flop type on a flop-by-flop basis for subsequent IC revisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pulse flops are used for high-speed signal paths, then speed is improved, but reliability deteriorates due to min-time problem and race conditions
Solution Approach 1:
The patent implements dynamic flop type selection where the same physical flop circuit can operate in different modes (master-slave or pulse flop) based on runtime conditions. The system dynamically determines whether to enable the master latch clock signal based on whether the flop is positioned in a critical path, allowing the circuit to adapt its behavior to prevent min-time problems while maintaining high speed where safe
Solution Approach 2:
The patent changes the operational parameters of the flop circuit by selectively enabling or disabling the master latch clock signal. When the master latch clock is disabled, the flop operates as a pulse flop with improved speed; when enabled, it operates as a master-slave flip-flop with improved reliability. This parameter change allows the system to optimize for either speed or reliability based on the specific circuit context
2Reliability
If conservative design approach is taken to prevent failures, then reliability is improved, but productivity deteriorates due to performance sacrifice
Solution Approach 1:
The patent performs preliminary simulation and analysis during the design phase to identify critical flops that are prone to min-time problems. By pre-determining which flops need master-slave operation and which can safely operate as pulse flops, the system avoids the need for costly post-silicon redesigns while maintaining high performance where appropriate
Solution Approach 2:
The patent creates a virtual model of the IC circuit and performs simulations on this copy before implementing the final design. By testing different flop type configurations in the simulation environment, the system can identify optimal designs without risking actual silicon implementations, thereby improving productivity by avoiding iterative physical prototyping
3Reliability
If redesign is performed after silicon implementation to fix flop issues, then reliability is improved, but loss of time increases due to costly redesign process
Solution Approach 1:
The patent implements a feedback mechanism where simulation results and timing analysis are used to automatically determine the appropriate flop type for each circuit location. This closed-loop approach ensures that the correct flop type is selected during the design phase, preventing the need for time-consuming post-silicon redesigns while maintaining high reliability
Data Source
AI summary
A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.