VLSI Interconnect Delay Estimation via Hierarchical Segmentation
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Solution Overview
Problem
Interconnect delay poses a significant limiting factor in integrated circuit performance, accounting for over 75% of total path delay in VLSI circuits, and existing methods for estimating this delay are time-consuming and inefficient.
Innovation Solution
A method for estimating interconnect delay in VLSI circuits involves calculating an off-path-point, projecting intersections, estimating total wire capacitance, and calculating delay contributions from both the source-to-sink path and off-path sinks, allowing for accurate and timely estimation of interconnect delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional interconnect delay estimation methods are used, then measurement precision may be adequate, but productivity is significantly reduced due to time-consuming calculations
Solution Approach 1:
The patent segments the interconnect network into hierarchical levels (individual interconnects, interconnect groups, and macro-blocks). Each segment is processed independently using pre-computed lookup tables, allowing parallel processing and significantly reducing overall estimation time while maintaining accuracy through systematic decomposition of the complex delay calculation problem.
Solution Approach 2:
The patent performs preliminary computation of delay parameters and stores them in pre-computed lookup tables before actual delay estimation is needed. These pre-computed values (including resistance, capacitance, and delay characteristics) are prepared in advance based on process geometry and interconnect topology, enabling rapid query-based estimation during circuit analysis without repeating complex calculations.
2Measurement precision
If detailed delay calculation considering all off-path sinks is performed, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent uses pre-computed lookup tables that contain copied and stored delay characteristics from previous detailed analyses. Instead of performing complex calculations considering all off-path sinks each time, the system copies previously computed delay values and uses them directly, significantly reducing calculation complexity while preserving the accuracy benefits of comprehensive analysis.
Solution Approach 2:
The patent transforms the complex multi-parameter delay calculation problem into a simplified parameter lookup process. By pre-computing delay characteristics as functions of relevant parameters (wire length, capacitance, resistance) and storing them in lookup tables, the system changes the computational approach from solving complex equations to retrieving pre-prepared parameter values, reducing calculation complexity while maintaining precision.
Data Source
AI summary
The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution.