Closed-Form State Space Models for VLSI Interconnects
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Solution Overview
Problem
Current methods lack an efficient and elegant way to generate exact original high-order state space models for general interconnect and transmission tree or net structures, leading to high computational complexity and instability in modeling and simulation of VLSI circuit performance.
Innovation Solution
A method and system for generating exact accurate state space models in closed form for general ITLTAN circuits using block-models based on topological structure, reducing computational complexity to O(N) or even O(1) for evenly distributed models, while ensuring numerical and pole stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional methods are used to generate state space models for general ITLTAN, then model accuracy is maintained, but computational complexity increases to O(N^2) or higher
Solution Approach 1:
The patent segments the complex ITLTAN circuit into basic components (branches, nodes, connections) and generates state space models for each segment using closed-form expressions. This modular approach reduces the overall computational complexity from O(N^2) to O(N) by avoiding the need to process the entire circuit as a single monolithic system.
Solution Approach 2:
The patent transforms the mathematical representation of the circuit by changing parameters from conventional matrix-based approaches to closed-form expressions based on circuit topology parameters (number of branches, nodes, connections). This parameter transformation enables linear computational complexity while maintaining model accuracy.
2Measurement precision
If detailed distributed circuit modeling is used for high-speed interconnects, then modeling accuracy improves, but analysis time increases significantly
Solution Approach 1:
The patent performs preliminary action by deriving closed-form state space models that directly represent the distributed circuit behavior without requiring iterative numerical methods. This preliminary formulation of the mathematical model enables fast analysis while maintaining the accuracy benefits of detailed distributed modeling.
Solution Approach 2:
The patent substitutes conventional numerical simulation methods with an analytical mathematical approach using closed-form expressions. This substitution replaces time-consuming iterative computation with direct calculation, significantly reducing analysis time while preserving modeling accuracy.
3Productivity
If model reduction methods are applied to reduce circuit order, then simulation speed increases, but model accuracy may deteriorate
Solution Approach 1:
The patent changes the parameter representation in model reduction by using closed-form expressions that preserve the essential dynamic characteristics of the original system. This parameter transformation allows for effective model reduction while maintaining accuracy in representing the dominant circuit behavior.
Data Source
AI summary
There is provided a set of methods for generating state space models of general VLSI interconnect and transmission lines, trees and nets by closed forms with exact accuracy and low computation complexity. The state space model is built by three types of models: the branch model, the connection model and the non-connection model, that are block matrices in closed forms, arranged with topology. The main features are the topology structure, simplicity and accuracy of the closed forms of the state space models {A,B,C,D} or {A,B,C}, computation complexity of O(N) in sense of scalar multiplication times, where N is the total system order, practice of the modeling, ELO model simplification, and their optimization. For evenly distributed interconnect and transmission lines, trees and nets, the closed forms of state space model have the computation complexity of O(1), i.e., only a fixed constant of scalar multiplication times.