VLSI Net Tracing via Unique NETID Markers
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Solution Overview
Problem
Electronic design automation (EDA) tools face challenges in verifying and tracing connections in very large scale integration (VLSI) integrated circuits, particularly in identifying electro-static discharge (ESD)/latch-up prevention (LUP) and high voltage issues due to the complexity and density of nets in VLSI IC designs.
Innovation Solution
A system and method for tracing nets in VLSI IC designs that allows users to select a portion of a net, set a marker, and trace the net through multiple layers, highlighting the connections and enabling the identification of erroneous connectivity, using a graphical user interface and unique NETIDs to identify and highlight the traced net.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If EDA tools are used to verify nets in VLSI IC designs, then design verification is enabled, but the complexity and density of nets make verification increasingly difficult
Solution Approach 1:
The patent segments the net tracing process into discrete steps: selecting a starting point, assigning a unique NETID, systematically tracing through connected conductive portions, and highlighting results. This segmentation breaks down the complex verification task into manageable segments that can be processed systematically, resolving the contradiction between verification reliability and tracing complexity.
Solution Approach 2:
The patent introduces an intermediary marker (unique NETID) that mediates between the user's selection and the net tracing process. This marker serves as a temporary identifier that guides the tracing algorithm through the complex net structure, enabling reliable verification without being overwhelmed by the complexity of direct net analysis.
2Measurement precision
If manual net tracing is performed in dense IC designs, then connectivity can be identified, but the process is time-consuming and error-prone
Solution Approach 1:
The patent performs preliminary actions by automatically assigning a unique NETID to the selected starting point before initiating the tracing process. This preliminary identification step streamlines the subsequent tracing operation, enabling faster and more accurate connectivity identification without manual intervention at each step, thus reducing time loss while maintaining precision.
Solution Approach 2:
The tracing system performs self-service by automatically following the conductive portions and assigning the NETID to all connected portions without requiring continuous user input. The system serves itself by systematically propagating the identifier through the net structure, reducing both time consumption and human error while maintaining high accuracy in connectivity identification.
3Adaptability or versatility
If existing EDA tools are used for net verification, then basic connectivity checking is possible, but identification of ESD/LUP and high voltage issues is difficult
Solution Approach 1:
The patent creates a universal net tracing system that can handle multiple verification tasks through a single unified interface. By enabling users to select any portion of a net and automatically tracing the entire connected structure with highlighted display, the system provides versatile capability for detecting various issues including ESD/LUP prevention and high voltage problems, overcoming the limitation of basic connectivity checking while reducing detection difficulty.
Data Source
AI summary
A system and method for tracing a net includes comparing an IC design against a marked portion of the IC design, and extracting a traced net that includes the marked portion from the IC design file. The method also includes displaying the traced net and storing at least one indicator along with information identifying the traced net.