Multiple Voltage Threshold Timing Analysis for VLSI Interconnects
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Solution Overview
Problem
Current timing and noise analysis methods for ultra-deep sub-micron VLSI circuits are inaccurate due to the assumption of purely capacitive loads, which fail to account for the resistive and inductive effects of modern VLSI interconnects, leading to inaccuracies in effective capacitance calculations and computational inefficiencies.
Innovation Solution
A multiple voltage threshold timing analysis method that uses a simulation of a controlled current source driver model with a linear interconnect RLC load, advancing on the voltage axis and eliminating the need for data transformation and smoothing, allowing for direct use of raw characterization data to derive crossing times and generate voltage waveforms indicative of the driving point voltage of logic gates loaded by interconnect circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional single effective capacitance calculation methods are used, then the timing analysis is computationally simple, but the accuracy deteriorates for RLC loads in modern VLSI technologies
Solution Approach 1:
The patent segments the continuous voltage transition into discrete voltage thresholds (e.g., 0.1Vdd, 0.2Vdd, ..., 0.9Vdd). Instead of using a single effective capacitance value for the entire transition, the method calculates separate effective capacitance values for each voltage threshold interval. This segmentation allows the analysis to capture the non-linear behavior of RLC loads more accurately while maintaining computational tractability through piecewise linear approximation.
Solution Approach 2:
The patent introduces a new dimension to the traditional timing analysis by considering multiple voltage thresholds simultaneously. Rather than analyzing a single propagation delay at 50% voltage, the method extends the analysis to track crossing times at multiple voltage levels (0.1Vdd through 0.9Vdd). This multi-dimensional approach captures the complex voltage-time behavior of RLC loads that cannot be represented by a single delay value.
2Measurement precision
If controlled current source models (ECSM/CCS) are used to improve accuracy, then the timing analysis becomes more accurate, but computational efficiency deteriorates due to data transformation and smoothing requirements
Solution Approach 1:
The patent extracts only the essential characterization data needed for timing analysis - specifically, the crossing times at multiple voltage thresholds. Instead of using full controlled current source models that require complex data transformation and smoothing operations, the method extracts discrete crossing time points from pre-characterization data and uses these directly in the timing analysis. This extraction approach maintains accuracy while eliminating unnecessary computational steps.
Solution Approach 2:
The patent creates a simplified representation of the complex controlled current source model by using discrete crossing time tables. Rather than working with continuous current waveforms that require transformation and smoothing, the method copies the essential timing information into discrete threshold-crossing time values that can be directly used in statistical timing analysis, significantly reducing computational overhead.
3Ease of manufacture
If pre-characterization is performed with purely capacitive loads, then the characterization process is simple and efficient, but the applicability deteriorates when analyzing circuits with RLC interconnects
Solution Approach 1:
The patent changes the parameters used to represent load effects. Instead of using a single effective capacitance value derived from pure capacitive loading, the method uses multiple effective capacitance values corresponding to different voltage thresholds. This parameter change allows the pre-characterization data (collected with simple capacitive loads) to be adapted to RLC interconnect scenarios by selecting appropriate capacitance values for each voltage threshold interval based on the actual load characteristics.
Data Source
AI summary
An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.