VLSI Yield Estimation via Spatial Correlation and Gaussian Modeling
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Solution Overview
Problem
Current methods for predicting the yield of integrated circuit designs, especially for very-large-scale integration (VLSI), are impractical due to the high number of elements and costs associated with manufacturing, making it difficult to determine the effects of design changes on yield before actual manufacturing.
Innovation Solution
The method involves building a Voronoi diagram of the design, converting it into a rectangular grid, computing and merging cell probabilities to account for spatial correlations, and using Gaussian random components to estimate yield, allowing for real-time prediction of yield without physical implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional yield estimation techniques are used for VLSI designs, then manufacturing accuracy can be maintained, but the design process becomes severely limited by time constraints and cannot operate in real-time
Solution Approach 1:
The VLSI design is divided into multiple smaller cells that are processed independently. Each cell's yield contribution is calculated separately, and then combined using spatial correlation functions. This segmentation allows the large-scale yield estimation problem to be broken down into manageable computational units that can be processed faster, enabling real-time interaction during the design phase while maintaining accuracy through proper correlation handling.
2Manufacturing precision
If physical implementation of design changes is performed to determine yield impact, then manufacturing precision can be verified, but the cost and time requirements become impractical for high-density circuits
Solution Approach 1:
Instead of physically implementing design changes to verify yield, the patent creates computational models that replicate the physical manufacturing process. These models use measured process data (focus, dose, aerial image) to simulate manufacturing outcomes and predict yield impacts of design changes. This copying approach allows multiple design iterations to be evaluated computationally at low cost while maintaining accuracy by grounding the models in actual process measurements.
Solution Approach 2:
The patent performs preliminary measurements of process parameters (focus, dose, aerial image) and builds computational models before actual manufacturing takes place. By predicting yield impacts through these pre-established models, designers can evaluate multiple design options and make informed decisions before committing to physical manufacturing, avoiding the need for costly and time-consuming trial productions.
3Productivity
If the number of elements in VLSI design increases to achieve high-density integration, then circuit functionality is improved, but conventional yield estimation techniques become computationally infeasible
Solution Approach 1:
The patent segments the large VLSI design into smaller computational cells, allowing yield estimation to scale with circuit size. By processing cells independently and combining results through spatial correlation functions, the computational complexity grows much more slowly than the number of elements, making yield estimation feasible for high-density VLSI designs with millions of elements.
Solution Approach 2:
The patent transforms the yield estimation problem from analyzing individual elements to analyzing spatial patterns of process parameters (focus, dose, aerial image). By changing the parameters from element-level to pattern-level analysis and using measured process data to drive the models, the computational complexity is reduced while maintaining accuracy for high-density circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables fast and accurate prediction of yield, allowing for real-time interactive adjustments to the design and reducing manufacturing limitations by providing a realistic estimate of yield loss and wafer yield, even for high-density circuits.
Implementation Method 1
A Gaussian random component of the focus and dose values is determined. The focus and dose values on the wafer are represented as a sum of a systematic component of the focus and dose values and the Gaussian random component of the focus and dose values.
Data Source
AI summary
A method for estimating yield of a wafer having a plurality of chips printed thereon is provided which includes the following steps. The chip design is divided into a plurality of rectangular cells. A process window is determined for each of the cells. The focus and dose values on the wafer are measured and used to determine a Gaussian random component of the focus and dose values. The focus and dose values on the wafer are represented as a sum of a systematic component of the focus and dose values and the Gaussian random component. Wafer yield is estimated based on a number of the chips for which at each point (x, y) the focus and dose values, as represented as the sum of the systematic component of the focus and dose values and the Gaussian random component, belong to a corresponding one of the process windows.