VM-to-VM Cache Fast Path via Virtual Queue Manager
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Solution Overview
Problem
Current virtualized environments face high latency and inefficiencies in VM-to-VM communication due to the reliance on conventional virtual switches, which hinder performance in data centers handling geographically dispersed data and emerging software-defined network (SDN) models.
Innovation Solution
The implementation of a VM-to-VM cache fast path that utilizes internal CPU cache to locally store and transmit network data, reducing latency and CPU cycles required for packet transfer, and the use of a virtual queue manager (VQM) to manage VM-VM allow entries and shared data buffers for optimized packet forwarding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional virtual switches are used for VM-to-VM communication, then traffic forwarding is achieved through software processing, but latency is high and throughput is limited
Solution Approach 1:
The patent extracts the packet forwarding function from the software virtual switch and implements it directly in hardware via the IOMMU. The IOMMU is configured with translation tables that map source and destination VM identifiers to buffer addresses, enabling direct hardware-based packet routing between VMs without software intervention, thus achieving low-latency high-speed communication
Solution Approach 2:
The patent introduces shared memory buffers as an intermediary mechanism between VMs. These buffers are allocated in a shared memory space accessible by multiple VMs, and the IOMMU directs packets to the appropriate buffer based on destination VM identifiers, enabling efficient packet exchange without traditional software switching
2Productivity
If software virtual switches are used for packet forwarding, then traffic can be routed between VMs, but CPU cycles are consumed for processing each packet
Solution Approach 1:
The patent implements a self-service packet forwarding mechanism where the IOMMU autonomously handles packet routing based on pre-configured translation tables. The system programs the IOMMU with source and destination VM identifiers mapped to buffer addresses, and the IOMMU automatically performs address translation and packet redirection without requiring CPU intervention for each packet, thereby eliminating continuous CPU cycle consumption
Solution Approach 2:
The patent performs preliminary configuration of the IOMMU translation tables before packet forwarding begins. The host system programs the IOMMU with mapping rules that associate VM identifiers with shared buffer addresses, so that when packets arrive, the IOMMU can immediately forward them without CPU processing, achieving high throughput with minimal ongoing CPU involvement
3Ease of operation
If shared memory buffers are used for VM-to-VM packet transfer, then direct hardware access is enabled, but memory access efficiency needs optimization
Solution Approach 1:
The patent assigns dedicated shared memory buffers to specific VM pairs for communication. Each buffer is locally optimized for its intended traffic flow, and the IOMMU directly maps VM identifiers to these specific buffer locations, enabling efficient localized memory access without conflicts or contention, thereby improving both speed and operational simplicity
Data Source
AI summary
Methods and apparatus for accelerating VM-to-VM Network Traffic using CPU cache. A virtual queue manager (VQM) manages data that is to be kept in VM-VM shared data buffers in CPU cache. The VQM stores a list of VM-VM allow entries identifying data transfers between VMs that may use VM-VM cache “fast-path” forwarding. Packets are sent from VMs to the VQM for forwarding to destination VMs. Indicia in the packets (e.g., in a tag or header) is inspected to determine whether a packet is to be forwarded via a VM-VM cache fast path or be forwarded via a virtual switch. The VQM determines the VM data already in the CPU cache domain while concurrently coordinating with the data to and from the external shared memory, and also ensures data coherency between data kept in cache and that which is kept in shared memory.