Virtual Machine Cache Write-Back Optimization for Secure Storage

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Solution Overview

Problem

In virtual machine systems with cache memory, write-back processing to secure storage areas is inefficient due to the need for context switches between secure and normal operating modes, leading to prolonged processing times when the normal OS is executing.

Innovation Solution

A virtual machine system with a cache memory that identifies data read from secure storage areas and uses an algorithm to reduce the frequency of write-backs to secure storage areas by prioritizing data from normal OS sleep state and avoiding secure OS sleep state data for write-backs, ensuring write-backs occur only when the processor is in the normal privileged mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the cache memory performs write-back processing to the secure storage area while the normal OS is executing, then the data in the cache memory is updated, but the processing time is prolonged due to context switches between secure and normal modes

Engineering Contradiction:
Improvedata consistencyVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing write-back processing to the secure storage area before the normal OS executes. The cache memory controller identifies data read from the secure storage area and performs write-back to the secure storage area in advance, before mode switching would be required. This eliminates the need for context switches during normal OS execution, resolving the contradiction between data consistency and processing time.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the processor switches to secure mode to perform write-back processing, then the data is written to the secure storage area, but the execution of the normal OS is interrupted

Engineering Contradiction:
Improvesecure storage accessVSAvoidOS execution efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the write-back processing function from the processor's normal execution flow and implements it in the cache memory controller. The cache memory controller independently identifies data read from the secure storage area and performs write-back to the secure storage area without requiring the processor to switch to secure mode. This separation allows the normal OS to execute continuously without interruption, resolving the contradiction between secure storage access and OS execution efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

3Adaptability or versatility

If the cache memory stores data from both secure and normal storage areas, then the cache utilization is improved, but the frequency of write-backs to secure storage area increases

Engineering Contradiction:
Improvecache memory utilizationVSAvoidwrite-back frequency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies local quality by differentiating the treatment of data based on its source. The cache memory controller identifies whether data was read from the secure storage area or the normal storage area and applies different write-back strategies. Data from the secure storage area is written back to the secure storage area only when necessary (before normal OS execution), while data from the normal storage area follows conventional write-back procedures. This selective approach maintains high cache utilization while minimizing write-back frequency to the secure storage area, resolving the contradiction between cache memory utilization and write-back frequency.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9218287B2Virtual computer system, virtual computer control method, virtual computer control program, recording medium, and integrated circuit
Publication Date: 2015.12.22 III HOLDINGS 12 LLC
  • US9218287B2 patent drawing
  • US9218287B2 patent drawing
  • US9218287B2 patent drawing

AI summary

A virtual machine system comprises: a processor for executing a secure operating system and a normal operating system; and a cache memory. The cache memory stores data in a manner that allows for identification of whether the data has been read from a secure storage area of an external main memory. The cache memory writes back data to the main memory in a manner that reduces the number of times data is intermittently written back to the secure storage area which occurs when the processor is executing the normal operating system.