Virtual Machine Interrupt Timer Control via Dynamic CPU Mode Switching
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Solution Overview
Problem
Existing virtual machine systems face performance issues due to high overhead in emulating interrupt timers for virtual CPUs, leading to data eviction from the translation lookaside buffer (TLB) or cache, especially in applications with strict latency requirements, as the interrupt timer of the physical CPU is not dynamically controllable by virtual CPUs.
Innovation Solution
A method to control the occupancy of a physical CPU's interrupt timer by a virtual CPU through dynamic switching of scheduling modes, allowing the virtual CPU to occupy the interrupt timer of the physical CPU, thereby minimizing emulation overhead and preventing data eviction from the TLB or cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the interrupt timer of the physical CPU is shared among multiple virtual CPUs through emulation, then resource utilization is improved, but the overhead of emulation increases and performance deteriorates
Solution Approach 1:
The patent implements dynamic switching between shared CPU mode and exclusive CPU mode based on application requirements. When an application with strict latency requirements is detected, the system switches to exclusive CPU mode where the virtual CPU directly occupies the physical CPU's interrupt timer, eliminating emulation overhead. This dynamic adaptation resolves the contradiction by allowing high resource utilization during normal operation while providing high performance when needed.
Solution Approach 2:
The system changes the allocation parameter of the interrupt timer from shared (emulated) to exclusive (direct occupation) based on the operational state and performance requirements. By changing the parameter of timer occupation mode, the system can optimize between resource utilization and performance for different workload scenarios.
2Reliability
If the interrupt timer is continuously operated to activate host processing and detect timeouts, then system reliability is improved, but data eviction from TLB or cache occurs leading to performance degradation
Solution Approach 1:
The patent dynamically controls the operation state of the interrupt timer based on the occupation mode. In exclusive CPU mode, when a virtual CPU directly occupies the interrupt timer, the system stops the interrupt timer to prevent unnecessary data eviction from TLB or cache, while still maintaining system reliability through proper timeout detection mechanisms. This resolves the contradiction by making the timer operation adaptive to the current mode.
Solution Approach 2:
The patent extracts the interrupt timer operation from continuous execution and conditions it based on occupation mode. By taking out the unnecessary timer operations when in exclusive mode, the system prevents harmful data eviction while maintaining essential reliability functions through selective timer control.
3Adaptability or versatility
If the interrupt timer of the physical CPU is emulated for virtual CPUs, then timer functionality is provided to virtual machines, but large emulation overhead affects applications with strict latency requirements
Solution Approach 1:
The system dynamically switches between emulated timer mode (for general compatibility) and direct occupation mode (for low latency requirements). When an application with strict latency requirements is detected, the system transitions to direct occupation mode where the virtual CPU directly uses the physical CPU's interrupt timer, eliminating emulation overhead and reducing latency. This resolves the contradiction by providing both timer functionality and low latency when needed.
Solution Approach 2:
The patent uses copying in the form of virtualization - creating a virtual interrupt timer that can either emulate the physical timer (for compatibility) or directly map to it (for performance). This copying mechanism allows the system to provide timer functionality to virtual machines while offering an optimization path that eliminates the copying/emulation overhead for time-sensitive applications.
Data Source
AI summary
The virtual machine system according to the present invention comprises: physical processors which each include an interrupt controller including an interrupt timer; and a virtualization unit which allocates computer resources including the physical processors and physical memories to a plurality of virtual machines. The virtualization unit allocates, to the plurality of virtual machines, virtual processors that are created by virtualizing the physical processors, sets one of the physical processors into either a shared processor mode or an exclusive processor mode, and then sets the interrupt timer of the physical processor that has been set into either the shared processor mode or the exclusive processor mode, into either a shared timer mode or an exclusive timer mode.