Secure Virtual Machine Interface Memory Access Control
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Solution Overview
Problem
Current systems face challenges in providing secure communication between virtual machines and devices, as traditional methods often disable security by mapping all guest memory, making it difficult to manage access and ensure flexibility in memory reallocation, leading to potential security risks.
Innovation Solution
The proposed solution involves a virtual machine associating different levels of security with devices, using a secure interface and buffer allocation to control access to guest memory, and employing a software input/output translation lookaside buffer (SWIOTLB) for enhanced security when necessary, allowing varying levels of access based on trust and security requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all guest memory is mapped to devices for communication, then communication efficiency is improved, but security is worsened
Solution Approach 1:
The patent segments guest memory into multiple regions with different access permissions. Instead of mapping all guest memory to devices, the system divides memory into secure regions (not accessible by devices) and non-secure regions (accessible by devices), allowing efficient communication in non-secure regions while protecting secure regions.
Solution Approach 2:
The patent applies different security characteristics to different parts of the memory system. Each memory region is assigned a security attribute (secure or non-secure) that determines device accessibility. This allows communication efficiency in non-secure regions while maintaining security in secure regions, resolving the contradiction between overall efficiency and security.
2Reliability
If security is enabled with restricted memory access, then security is improved, but flexibility in memory reallocation is worsened
Solution Approach 1:
The patent implements dynamic security region management where the hypervisor can adjust which memory regions are marked as secure or non-secure based on runtime requirements. This allows the system to maintain security constraints while flexibly reallocating memory regions as needed, resolving the contradiction between security and flexibility.
Solution Approach 2:
The patent changes the security parameter (secure/non-secure attribute) of memory regions dynamically. By modifying the security attribute of specific memory regions rather than applying a fixed security policy to all memory, the system can enforce security where needed while maintaining flexibility in other regions, allowing adaptive memory reallocation.
3Reliability
If device access to guest memory is restricted, then security is improved, but ease of operation is worsened
Solution Approach 1:
The patent implements automatic security checking by the hypervisor for device access requests. Instead of requiring complex manual configuration or intervention, the hypervisor automatically checks whether requested memory regions are secure or non-secure and grants or denies access accordingly, maintaining security while simplifying operation.
Solution Approach 2:
The patent provides feedback mechanisms where the hypervisor monitors device access requests and automatically responds based on the security status of target memory regions. This automated feedback loop maintains security constraints without requiring manual intervention, preserving ease of operation while ensuring security.
Data Source
AI summary
A system includes a memory and a processor. The memory is in communication with the processor and configured to initialize a secure interface configured to provide access to a virtual machine (VM) from a device, where the VM is associated with a level of security. A buffer is allocated and associated with the secure interface, where the level of security of the VM indicates whether the device has access to guest memory of the VM via the buffer. The buffer is then provided to the device. Inputs/outputs (I/Os) are sent between the device and the VM using the secure interface.