VM Migration Logic for Uncorrectable Memory Errors

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Solution Overview

Problem

Existing live migration implementations fail when uncorrectable memory errors are detected in the physical memory backing virtual machines, particularly in deployments using byte-addressable persistent memory, leading to migration failures and hypervisor crashes due to the higher error rates and persistent memory mappings.

Innovation Solution

The implementation of uncorrectable memory error-tolerant migration logic in hypervisors allows for the safe reading and copying of guest memory pages, transmitting error metadata to the destination host, and simulating uncorrectable memory errors on the destination side to maintain VM consistency and prevent crashes during live migration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If live migration is implemented using conventional methods, then migration can be performed with simple logic, but migration fails when uncorrectable memory errors are detected in physical memory

Engineering Contradiction:
Improvemigration success rateVSAvoidmigration logic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by checking for uncorrectable memory errors in the source physical memory before initiating the live migration process. The hypervisor identifies affected memory pages in advance, excludes them from migration, and prepares error metadata beforehand. This prevents migration failures caused by undetected memory errors while maintaining a relatively simple migration workflow.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces error metadata as an intermediary element that carries information about uncorrectable memory errors from the source host to the destination host. This metadata acts as a mediator that enables the destination hypervisor to simulate the same error conditions, ensuring VM consistency without requiring complex direct error propagation mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If byte-addressable persistent memory is used, then memory capacity and persistence are improved, but uncorrectable memory error rate increases significantly

Engineering Contradiction:
Improvememory capacityVSAvoidmemory error rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent extracts the problematic memory pages with uncorrectable errors from the migration process. By identifying and excluding affected pages before migration, the system prevents these high-error pages from being transferred to the destination host, thereby maintaining VM reliability while still utilizing the high-capacity persistent memory for unaffected pages.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent converts the harmful effect of uncorrectable memory errors into a beneficial filtering mechanism. By detecting and marking erroneous pages, the system uses this error information to improve migration reliability through selective exclusion, turning the presence of errors into an opportunity for more robust error handling and VM protection.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Stability of the object's composition

If memory error simulation is implemented on destination host, then VM consistency is maintained, but additional processing overhead is introduced

Engineering Contradiction:
ImproveVM consistencyVSAvoidprocessing overhead
Core Design Contradiction:
Stability of the object's compositionVSUse of energy by moving object

Solution Approach 1:

The patent uses copying by transmitting error metadata from the source host to the destination host instead of copying the actual error states. This metadata contains minimal information about affected memory pages, allowing the destination hypervisor to simulate errors efficiently with low processing overhead while maintaining complete VM consistency.

Inventive Principle:
Principle #26Copying

4Productivity

If physical memory mappings persist across host reboots, then memory allocation efficiency is improved, but VM mobility is lost due to error persistence

Engineering Contradiction:
Improvememory allocation efficiencyVSAvoidVM mobility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent applies segmentation by dividing the physical memory into affected and unaffected pages based on error metadata. This segmentation allows the system to maintain persistent mappings for the majority of healthy memory pages while isolating and excluding only the erroneous pages from migration, thereby preserving both memory allocation efficiency and VM mobility.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11960357B2Managing the migration of virtual machines in the presence of uncorrectable memory errors
Publication Date: 2024.04.16 VMWARE INC
  • US11960357B2 patent drawing
  • US11960357B2 patent drawing
  • US11960357B2 patent drawing

AI summary

Techniques for migrating virtual machines (VMs) in the presence of uncorrectable memory errors are provided. According to one set of embodiments, a source host hypervisor of a source host system can determine, for each guest memory page of a VM to be migrated from the source host system to a destination host system, whether the guest memory page is impacted by an uncorrectable memory error in a byte-addressable memory of the source host system. If the source host hypervisor determines that the guest memory page is impacted, the source host hypervisor can transmit a data packet to a destination host hypervisor of the destination host system that includes error metadata identifying the guest memory page as being corrupted. Alternatively, if the source host hypervisor determines that the guest memory page is not impacted, the source host hypervisor can attempt to read the guest memory page from the byte-addressable memory in a memory exception-safe manner.