Virtual Machine Paging Cache Protection Optimization

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Solution Overview

Problem

In virtualization technology, efficiently mapping guest paging structures to Virtual Machine Monitor (VMM) paging structures is challenging due to overhead-intensive page faults and the need for sufficient protection of paging tables, which affects the performance of virtualized operating systems.

Innovation Solution

A system and method for optimizing page faults and protecting paging tables by using hardware-supported real paging structures, caching connection structures between guest and real physical addresses, and employing tie descriptors and CR3 cache to manage page mappings and synchronization of access and dirty bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If guest paging structures are mapped to VMM paging structures, then virtualization is enabled, but page faults become frequent and overhead increases

Engineering Contradiction:
Improvevirtualization capabilityVSAvoidperformance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent creates a copy of the guest paging structures in the VMM's shadow page tables. This shadow copy allows the VMM to track and manage page mappings without constantly interfering with the guest OS, reducing page faults and overhead while maintaining virtualization functionality.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent pre-establishes shadow page tables and connection structures before the guest OS needs to access pages. By preparing these mappings in advance, the system avoids frequent page faults and reduces the overhead of handling page translations during guest OS operation.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If paging structures are protected, then security is improved, but page fault handling becomes more complex

Engineering Contradiction:
Improvepaging table protectionVSAvoidpage fault handling complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces connection structures as intermediaries between the guest paging structures and the VMM's shadow page tables. These connection structures act as mediators that track the relationship between guest and real pages, enabling protection while simplifying fault handling through pre-established mapping relationships.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements feedback mechanisms through connection structures that track page access patterns and mapping status. This feedback allows the system to optimize protection strategies and reduce unnecessary page fault handling complexity by understanding actual usage patterns.

Inventive Principle:
Principle #23Feedback

3Productivity

If multiple Virtual Machines run simultaneously, then resource utilization increases, but memory allocation becomes more difficult

Engineering Contradiction:
Improveserver consolidation efficiencyVSAvoidmemory allocation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the memory management responsibilities by creating separate shadow page tables for each Virtual Machine. This segmentation allows independent memory allocation and management for each VM while maintaining overall system coordination through the connection structures that map guest pages to physical pages.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8438363B1Optimization of paging cache protection in virtual environment
Publication Date: 2013.05.07 PARALLELS INT GMBH
  • US8438363B1 patent drawing
  • US8438363B1 patent drawing
  • US8438363B1 patent drawing

AI summary

A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures. A Virtual Machine (VM) is running guest code and has at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space. At least some of the guest paging structures are mapped to the real paging structures. A cache of connection structures represents cached paths to the real paging structures. The mapped paging tables are protected using RW-bit. A paging cache is validated according to TLB resets. Non-active paging tree tables can be also protected at the time when they are activated. Tracking of access (A) bits and of dirty (D) bits is implemented along with synchronization of A and D bits in guest physical pages.