Virtual Machine Replication via Host-to-Host PCIe Interconnections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Legacy virtual machine replication techniques over IP packet-switched networks suffer from high latencies and inefficiencies, leading to asynchronous copying issues and undesirable scenarios where memory states between virtual machines are not identical, causing performance problems and potential failures.
Innovation Solution
Implementing hardware-assisted memory-to-memory copying using host-to-host PCIe interconnections and software composable infrastructure to replicate virtual machine states directly between computing nodes, reducing the reliance on network bandwidth and CPU cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory pages are copied over IP packet-switched network, then virtual machine replication is achieved, but high latency and network bandwidth consumption occur
Solution Approach 1:
The patent introduces a PCIe switch as an intermediary device between the source and destination hosts. The PCIe switch fabric acts as a mediator that enables direct memory access between the two hosts through PCIe roots complex devices, bypassing the IP packet-switched network. This intermediary PCIe infrastructure provides a dedicated high-speed path for memory replication, resolving the latency issue while maintaining replication reliability.
Solution Approach 2:
The patent replaces the software-based IP packet-switching mechanism with a hardware-based PCIe direct memory access mechanism. By substituting the network stack and protocol processing with direct hardware-level memory access through PCIe, the system eliminates the overhead and latency associated with network packet processing, achieving faster and more reliable virtual machine replication.
2Productivity
If high bandwidth IP packet-switching components are used, then copying speed improves, but CPU cycles and memory usage increase due to protocol processing
Solution Approach 1:
The patent implements self-service by enabling direct memory-to-memory copying through PCIe DMA (Direct Memory Access). The PCIe roots complex devices and PCIe switch handle the data transfer autonomously without requiring CPU intervention for packet processing, protocol handling, or data movement. This self-service mechanism allows high copying speed while minimizing CPU cycle consumption, as the hardware infrastructure handles the replication task independently.
3Stability of the object's composition
If virtual machine memory state is replicated synchronously, then data consistency is improved, but network bandwidth requirements increase
Solution Approach 1:
The PCIe switch fabric serves as an intermediary that provides a dedicated high-speed path for synchronous memory replication. This dedicated hardware path enables maintaining memory state consistency between source and destination virtual machines without consuming excessive network bandwidth, as the PCIe infrastructure provides sufficient bandwidth specifically for this replication purpose without competing with other network traffic.
Data Source
AI summary
Methods, systems, and computer code for CPU-oblivious replication of memory of a virtual machine from one computing node to another computing node over PCIe hardware. A source virtual machine is designated to be replicated from a source computing node of a multi-node computing cluster to a target computing node of the multi-node computing cluster. When a CPU of the source computing node decodes an instruction that causes a change to contents of a memory location of the source virtual machine, the changed contents of the memory location is copied into a memory address of a target virtual machine by using hardware capabilities of two or more PCIe devices to synchronously clone data from the source computing node to the target computing node. The CPU of the source computing node obliviously waits to execute a further instruction of the source virtual machine until accomplishment of the cloned memory WRITE transaction.