Inter-VM Communication via Shared Memory Mapping
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Solution Overview
Problem
Existing inter-virtual machine (VM) communication mechanisms, particularly in GPU cloud environments, face inefficiencies due to high costs associated with moving data between system memory and local graphics memories, leading to slow read times and reduced throughput, as device local memory is often uncacheable.
Innovation Solution
Implementing a device-level memory sharing mechanism that avoids unnecessary CPU copies by mapping virtual graphics memories to system memory, allowing direct access and sharing between VMs, utilizing GPU page tables controlled by a hypervisor to facilitate fast inter-VM communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is moved between system memory and local graphics memories using existing inter-VM communication mechanisms, then data exchange between VMs is achieved, but read time increases and throughput decreases due to heavy copy costs and uncacheable memory mapping
Solution Approach 1:
The patent merges the memory spaces of multiple VMs by establishing a shared memory region that is physically located in system memory but logically accessible as local graphics memory by multiple VMs simultaneously. This eliminates the need for data copying between separate local graphics memories and system memory, as the shared memory region serves as both system memory and local graphics memory for participating VMs.
Solution Approach 2:
The patent introduces a shared memory region as an intermediary between VMs that need to exchange data. This shared memory region is managed by the virtualization layer and provides a buffer that VMs can access efficiently. The shared memory region acts as a mediator that enables direct VM-to-VM data transfer without requiring data to be copied through system memory in the traditional manner.
2Ease of operation
If device local memory is mapped as uncacheable to enable direct access, then memory access is possible, but read operations become very slow reducing overall throughput
Solution Approach 1:
The patent combines the benefits of local graphics memory (fast access) with system memory (cacheable) by making the shared memory region physically located in system memory but accessible to VMs as if it were local graphics memory. This merging allows the memory to be cached while maintaining direct access capabilities for VMs.
Solution Approach 2:
The patent changes the memory mapping parameters by configuring the shared memory region to be cacheable in system memory while simultaneously presenting it to VMs as local graphics memory. This parameter change transforms the memory characteristics from uncacheable to cacheable, dramatically improving read speeds and throughput while maintaining ease of access.
3Power
If multiple VMs are hosted on the same node with local graphics memories to achieve best performance, then processing performance is improved, but data exchange between VMs becomes inefficient due to heavy copy overhead
Solution Approach 1:
The patent merges the local graphics memories of multiple VMs into a single shared memory region located in system memory. This allows VMs to maintain their local memory access patterns while eliminating the physical duplication of data in separate local graphics memories. Data exchanged between VMs resides in the shared memory region and does not need to be copied between separate local memories and system memory.
Solution Approach 2:
The shared memory region serves multiple functions simultaneously: it acts as system memory for the host, local graphics memory for multiple VMs, and a shared communication buffer for inter-VM data exchange. This multi-functionality eliminates the need for separate communication pathways and copy operations between VMs with local graphics memories.
Data Source
AI summary
An apparatus and method are described for efficient inter-virtual machine (VM) communication. For example, an apparatus comprises inter-VM communication logic to map a first specified set of device virtual memory addresses of a first VM to a first set of physical memory addresses in a shared system memory and to further map a second specified set of device virtual memory addresses of a second VM to the first set physical memory addresses in the shared system memory.