Virtual Machine Task Distribution Across Heterogeneous Processors

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Solution Overview

Problem

Computing devices with multiple processors executing different instruction set architectures face inefficiencies in resource utilization, leading to suboptimal execution times and power consumption, as main and auxiliary processors often operate below or above utilization thresholds without efficient task distribution.

Innovation Solution

A system that initializes a virtual machine on both main and auxiliary processors, allowing the auxiliary processor to execute instructions from the main processor using a different instruction set architecture, and updates context data, thereby enabling efficient task distribution and reducing power consumption by leveraging underutilized resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple processors with different instruction set architectures are used, then processing capability and task distribution efficiency are improved, but system complexity increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a virtual machine as an intermediary layer between the main processor and auxiliary processor. This virtual machine manages instruction translation and task distribution, allowing processors with different instruction set architectures to communicate and cooperate efficiently. The virtual machine acts as a mediator that handles the complexity of cross-architecture communication, thereby improving productivity without requiring direct complex interactions between heterogeneous processors.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If task distribution between main and auxiliary processors is optimized, then execution time is reduced, but resource monitoring and management complexity increases

Engineering Contradiction:
Improveexecution timeVSAvoidresource management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the system continuously monitors processor utilization indicators and dynamically adjusts task distribution. The virtual machine receives feedback about the current state of main and auxiliary processors, and based on this feedback, it optimizes task allocation to balance workloads. This feedback loop enables reduced execution time through efficient task distribution while automating the resource management process, thereby limiting the increase in management complexity.

Inventive Principle:
Principle #23Feedback

3Use of energy by moving object

If auxiliary processor is utilized to execute instructions, then power consumption is reduced, but instruction set architecture compatibility challenges arise

Engineering Contradiction:
Improvepower consumptionVSAvoidinstruction set architecture compatibility
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The patent employs parameter changes by implementing instruction translation mechanisms that convert instructions from one instruction set architecture to another. When the auxiliary processor needs to execute instructions from the main processor, the virtual machine translates the instruction parameters and format to be compatible with the auxiliary processor's architecture. This allows the system to utilize the auxiliary processor for energy-efficient execution while maintaining instruction set architecture compatibility through dynamic parameter transformation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12067412B2Executing an application with multiple processors
Publication Date: 2024.08.20 INTEL CORP
  • US12067412B2 patent drawing
  • US12067412B2 patent drawing
  • US12067412B2 patent drawing

AI summary

In one example, a system for executing applications can include a main processor to initialize a virtual machine to execute an application. The main processor can also determine a main utilization indicator of the main processor is above a threshold and an auxiliary utilization indicator of an auxiliary processor is below a threshold, wherein the auxiliary processor is based on an auxiliary instruction set architecture. Additionally, the main processor can transmit an instruction from the application to the auxiliary processor for execution and update context data for the application in response to receiving an execution result from the auxiliary processor.