VMC Frame Clock Synchronization via Phase-Lock Loop
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Solution Overview
Problem
Redundant digital flight control systems in UAVs face challenges in synchronizing frame clocks across multiple Vehicle Management Computers (VMCs) to ensure seamless control transfer and minimize time skews, especially with varying numbers of active VMCs and potential failures.
Innovation Solution
A method involving a phase-lock loop algorithm that adjusts the frame clock period of each VMC based on the largest phase difference in data packet arrival times across Cross Channel Data Links, ensuring all VMCs operate within a microsecond of each other, using a damping ratio to manage synchronization speed and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-redundant VMC architecture is used to decrease the probability of catastrophic loss, then system reliability is improved, but synchronizing frame clocks becomes more complex
Solution Approach 1:
The patent implements a feedback mechanism where each VMC continuously monitors the arrival time of data packets from other VMCs, calculates phase differences, and adjusts its frame clock period accordingly. This closed-loop control ensures that all VMCs converge to a common time base, resolving the synchronization complexity in multi-redundant architectures while maintaining high reliability
Solution Approach 2:
The patent uses data packet timestamps as an intermediary to indirectly synchronize frame clocks across multiple VMCs. Instead of directly synchronizing clocks, the system uses the timestamps embedded in exchanged data packets to measure phase differences and guide clock adjustments, simplifying the synchronization process in redundant systems
2Reliability
If frame clocks are synchronized across multiple VMCs to enable smooth control transfer, then control transfer reliability is improved, but time skew management becomes more difficult
Solution Approach 1:
The patent performs preliminary synchronization actions by continuously adjusting frame clock periods based on measured phase differences before control transfer issues arise. This proactive synchronization ensures that when control transfer is needed, the VMCs are already synchronized, eliminating time skew problems during critical control transitions
3Measurement precision
If the frame clock period is adjusted to reduce phase difference, then synchronization accuracy is improved, but synchronization stability may deteriorate due to oscillations
Solution Approach 1:
The patent implements dynamic adjustment of frame clock periods where the synchronization target phase angle is continuously updated based on the current phase difference measurement. This dynamic approach allows the system to adapt to changing conditions while maintaining stability through continuous convergence toward the common time base, preventing oscillations that would occur with static adjustment
Data Source
AI summary
A method for synchronizing frame clocks in a plurality of processors comprises the steps of sending data packets from each of the processors to each of the other processors wherein each of the processors receives the data packets and identifies two of the data packets having the largest phase difference. The largest phase difference is used to determine a target synchronization phase angle, and the period of a frame clock is adjusted so that the frame clock approaches the target synchronization phase angle.