VM-ID Interface Access Control for Multi-Core Address Ranges
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Solution Overview
Problem
Existing multi-core processing systems face inefficiencies in managing access rights for virtual machines due to the complexity and power consumption associated with memory management units and memory protection units, particularly in low-cost and low-power solutions.
Innovation Solution
Implement a system where each processing core and resource has a master and slave interface with registers storing virtual machine IDs, allowing the slave interface to determine and enforce access rights based on these IDs, reducing the need for extensive translation tables and caching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory management units and memory protection units are used to manage access rights for virtual machines, then access control capability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the access control functionality from complex memory management units and memory protection units, implementing it instead through simple interface circuits (master interfaces and slave interfaces) with registers that store virtual machine IDs. This separation removes the need for extensive translation tables and caching mechanisms while maintaining access control capability.
Solution Approach 2:
The patent replaces expensive, complex memory management units with simple, low-cost interface circuits that use minimal hardware resources. The master and slave interfaces employ straightforward register comparisons rather than complex translation lookaside buffers, providing an economical solution suitable for low-cost and low-power systems.
2Reliability
If memory management units and memory protection units are used to manage access rights for virtual machines, then access control capability is improved, but power consumption increases
Solution Approach 1:
The patent extracts the access control functionality from power-intensive memory management units, implementing it through low-power interface circuits that simply compare virtual machine IDs stored in registers. This eliminates the need for energy-consuming translation tables and caching operations while maintaining security.
Solution Approach 2:
The patent replaces power-consuming memory management units with simple, low-power interface circuits that perform basic register comparisons. This provides an energy-efficient solution that is particularly suitable for battery-powered and low-power embedded systems.
3Measurement precision
If extensive translation tables and caching are used for access right management, then access control precision is improved, but device complexity increases
Solution Approach 1:
The patent removes the need for extensive translation tables and caching mechanisms by implementing access control directly at the interface level. The master and slave interfaces use simple register comparisons to enforce access rights, achieving precise control without the overhead of complex translation structures.
4Device complexity
If simple interface circuits with register comparison are used for access control, then device complexity is reduced, but access control capability may be limited
Solution Approach 1:
The patent segments the access control function into distributed components at each master and slave interface. Each interface independently compares virtual machine IDs in its registers, providing decentralized access control that maintains system security while avoiding the need for centralized complex management units.
Solution Approach 2:
The master and slave interfaces perform access control autonomously by comparing virtual machine IDs stored in their own registers. This self-service mechanism eliminates the need for external memory management units to enforce access rights, achieving both simplicity and effective access control.
Data Source
AI summary
A communication system couples a plurality of processing cores together, each having an associated register storing a virtual machine ID, which is inserted into requests sent by the respective processing core. A master circuit has associated a master interface circuit, wherein the master interface circuit has associated register for storing a second virtual machine ID, which is inserted into requests sent by the master circuit. A slave circuit has associated a slave interface circuit configured to selectively forward read or write requests addressed to an address sub-range. The slave interface circuit has associated a third register storing a third virtual machine ID associated with the address sub-range and is configured to receive a request addressed to the address sub-range, extract from the request a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID, and then either forwards or rejects the request.