Vmin Retention Detector for Digital ICs

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Solution Overview

Problem

The challenge lies in detecting and tracking the minimum operational voltage (Vmin) for digital integrated circuits to ensure reliable data retention, as existing technologies struggle with process parameter variations and energy efficiency at low supply voltages, where circuits may fail to retain data or flip their states.

Innovation Solution

An in-situ, symmetric logic Vmin retention voltage detection (RVD) circuit is implemented for sequential units, using dual independent logic units and tunable loads to predict data retention failure and adjust the Vmin threshold, integrated within the dynamic voltage and frequency scaling loop of the processor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If supply voltage is reduced to maximize energy efficiency, then energy consumption decreases, but data retention reliability deteriorates as circuits may fail to retain data or flip states at minimum supply voltages

Engineering Contradiction:
Improveenergy consumptionVSAvoiddata retention reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent implements preliminary action by using a retention voltage detector circuit that continuously monitors and detects the minimum operational voltage (Vmin) before data retention failure occurs. The detector includes a sequential unit that stores test data and a detection unit that compares actual supply voltage against the detected Vmin threshold, enabling the system to take preventive action before data loss happens, thus resolving the contradiction between energy efficiency and data retention reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies feedback by creating a closed-loop monitoring system where the retention voltage detector continuously feeds back the detected Vmin information to the power management unit. This feedback mechanism allows dynamic adjustment of power supply voltage to maintain operation above the safe threshold while maximizing energy efficiency, thereby resolving the contradiction between reducing energy consumption and ensuring data retention reliability

Inventive Principle:
Principle #23Feedback

2Use of energy by moving object

If supply voltage scaling is used to reduce energy consumption, then energy efficiency improves, but the adverse impact of process parameter variations on silicon performance and reliable operation increases

Engineering Contradiction:
Improveenergy consumptionVSAvoidprocess parameter variation sensitivity
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent applies local quality by implementing a dedicated retention voltage detector circuit with sequential units and detection units specifically designed to monitor voltage thresholds. This localized monitoring capability allows precise detection of Vmin under actual process conditions, enabling the system to compensate for process parameter variations and maintain reliable operation while using aggressive voltage scaling for energy efficiency

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses parameter changes by dynamically detecting and tracking the minimum operational voltage threshold under varying process conditions. The retention voltage detector adjusts its monitoring based on actual process parameter variations, allowing the system to maintain precise voltage control adaptively, thus resolving the contradiction between energy efficiency through voltage scaling and sensitivity to process variations

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10018674B2V<sub>min </sub>retention detector apparatus and method
Publication Date: 2018.07.10 INTEL CORP
  • US10018674B2 patent drawing
  • US10018674B2 patent drawing
  • US10018674B2 patent drawing

AI summary

Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.