VNA on Chip Direct Conversion Architecture
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Solution Overview
Problem
Traditional vector network analyzers (VNAs) are complex, large, and expensive due to their reliance on multiple heterodyne receivers and frequency conversion methods, which introduce unwanted spurs and require extensive filtering, limiting their accessibility and affordability.
Innovation Solution
A vector network analyzer integrated circuit (VNA IC) that includes a clock generator, signal conditioning unit, and quadrature generator for direct conversion, reducing the need for multiple receivers and intermediate frequency stages, allowing for a compact and cost-effective VNA system with improved signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional heterodyne receivers are used for frequency conversion, then measurement capability is achieved, but device complexity and size increase significantly
Solution Approach 1:
The patent extracts and eliminates the intermediate frequency (IF) conversion stage from the traditional heterodyne receiver architecture. By using direct conversion, the mixer outputs are fed directly to baseband filters and ADCs, removing the need for IF filters, IF amplifiers, and associated frequency synthesisers, thereby significantly reducing device complexity while maintaining measurement capability
Solution Approach 2:
The patent implements a single shared IF filter that serves multiple receive channels simultaneously. This universal filter structure allows one filter to handle frequency planning for multiple receivers, reducing the overall number of filters needed and simplifying the frequency synthesis requirements across the system
2Measurement precision
If multiple heterodyne receivers and frequency synthesizers are used, then frequency locking and measurement accuracy are improved, but unwanted spurs are introduced
Solution Approach 1:
The patent removes multiple frequency synthesizers and heterodyne conversion stages from the system. By implementing direct conversion with a single shared IF filter, the architecture eliminates the multiple mixing operations that generate spurious signals, thereby reducing unwanted spurs while maintaining frequency locking capability through a simplified synthesis approach
Solution Approach 2:
The shared IF filter serves multiple receive channels, providing frequency selectivity and rejection for all channels simultaneously. This universal filtering approach reduces the need for multiple dedicated filters and synthesizers per channel, thereby reducing the generation of unwanted spurs across the system
3Adaptability or versatility
If traditional VNA architecture with multiple receivers is used, then measurement functionality is comprehensive, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple receiver functions into a single integrated receiver chip that contains multiple receive channels sharing common components. The shared IF filter, common frequency synthesizer, and integrated ADCs are combined on one chip, reducing the total component count and manufacturing cost while maintaining comprehensive measurement functionality across multiple channels
Solution Approach 2:
The integrated receiver chip provides multi-functional capability with multiple receive channels that can handle different frequency ranges and measurement types. This universal chip design eliminates the need for separate discrete receiver modules, thereby reducing manufacturing complexity and cost while maintaining comprehensive VNA measurement capabilities
4Adaptability or versatility
If traditional VNA system is implemented, then full measurement features are available, but physical space occupation is large
Solution Approach 1:
The patent combines multiple receiver channels, frequency synthesizers, filters, and signal processing functions into a single integrated receiver chip. This consolidation merges what would traditionally be separate discrete components into one compact unit, providing full measurement features while dramatically reducing the physical space required for the VNA system
Solution Approach 2:
The integrated receiver chip nests multiple functional subsystems within a single chip structure. Receive channels, frequency synthesis, filtering, and digital processing are nested together in a hierarchical integration scheme, allowing full measurement functionality to be contained in a compact form factor that occupies minimal physical space
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the construction of a full-featured VNA at a fraction of the cost and physical space of traditional systems, with enhanced measurement accuracy and reduced noise interference through direct conversion and efficient signal processing.
Implementation Method 1
The signal conditioning unit may generate a filtered first clock signal and the stimulus signal
Implementation Method 2
These I and Q clock signals may be used with receiver mixers to facilitate direct conversion
Implementation Method 3
The receivers on both ports can receive the measurements and generate proportional DC signals by using direct conversion
Implementation Method 4
its VSWR bridge may function as a directional device (and distinguish between the applied and reflected powers)
Implementation Method 5
The VNA IC can provide the DC measurements to a processing unit after being low pass filtered and/or digitized
Data Source
AI summary
A front end of a vector network analyzer (VNA) on an integrated circuit includes a clock generator and two ports. The VNA couples to a device under test (DUT) using the two ports. Each port may include a plurality of receivers and a VSWR bridge, and can be configured as either an input or an output. The clock generator can generate a stimulus signal, an in-phase I clock signal, and a quadrature-phase Q clock signal. The output port provides the stimulus signal to the DUT and measures both reference and reflected power from the DUT, such as by utilizing two receivers by using direct conversion and the I and Q clock signals. The input port measures transmitted power through the DUT using a second VSWR bridge and one of its receivers by using direct conversion along with the I and Q clock signals. The VNA IC can provide S-parameter measurements to a processing unit for further processing and/or analysis to compute the DUT S-parameters.