3D VNAND Channel Charge Control via PEALD Dopant Diffusion
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Solution Overview
Problem
The 3D VNAND flash memory devices face challenges with non-uniform charge distribution and reduced charge in the vertically stacked polysilicon channel layer, leading to operational issues due to current leakage and limitations in integration.
Innovation Solution
A semiconductor device structure is developed with alternately stacked gate and interlayer insulation layers, including a non-conductive oxide-nitride-oxide layer, a polysilicon channel layer, a silicon oxide barrier layer, a phosphosilicate glass source layer, and a capping layer, formed using atomic layer deposition methods to prevent charge reduction and imbalance, with specific gas-supplying cycles and heat treatment to diffuse dopants effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional 2-dimensional gate structure is used, then the device structure is simple, but the degree of integration cannot be improved due to current leakage in the channel
Solution Approach 1:
The patent transitions from a conventional 2-dimensional gate structure to a 3-dimensional vertical gate structure. The gate electrode extends vertically through the substrate, creating a vertical channel region that increases the effective channel area without increasing the planar footprint. This dimensional change enables higher degree of integration while maintaining proper charge distribution and reducing current leakage issues.
2Productivity
If a vertically stacked polysilicon channel layer is used in 3D VNAND, then the degree of integration is improved, but charge distribution becomes non-uniform causing operational issues
Solution Approach 1:
The patent introduces a doping layer with different doping concentration than the channel layer, positioned adjacent to the vertical channel region. This creates local quality variation where the doping layer provides enhanced charge distribution control in specific regions. The doping layer may have higher or lower doping concentration depending on the required charge distribution profile, ensuring uniform charge distribution throughout the vertical channel and preventing operational issues.
3Ease of manufacture
If the channel layer is formed without additional doping layers, then the manufacturing process is simple, but charge reduction occurs in the channel layer
Solution Approach 1:
The patent forms a doping layer adjacent to the vertical channel region before final channel layer formation or in conjunction with it. This preliminary doping action ensures that charge carriers are available in the channel region from the outset, preventing charge reduction during device operation. The doping layer serves as a charge reservoir that maintains proper charge levels in the channel, ensuring reliable device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents charge reduction and ensures balanced charge distribution in the channel layer of 3D vertical structures, enhancing the operational reliability and integration capabilities of VNAND flash memory devices.
Implementation Method 1
repeating a first gas-supplying cycle for forming a barrier layer to be perpendicular to the surface of the substrate at a lateral surface of the channel layer; and repeating a second gas-supplying cycle for forming a source layer at a lateral surface of the barrier layer, wherein the first gas-supplying cycle and the second gas-supplying cycle may be performed by an atomic layer deposition method
Implementation Method 2
activating the oxygen gas with plasma during the third time
Implementation Method 3
with specific gas-supplying cycles and heat treatment to diffuse dopants effectively
Data Source
AI summary
Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-dimensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.