Vertical NAND Charge Blocking Layer Crystallization
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Solution Overview
Problem
Vertical NAND (VNAND) flash memory devices face challenges with high program/erase voltages, small memory window, and data retention issues due to the difficulty in crystallizing charge blocking layers, which affect the integration and performance of non-volatile memory devices.
Innovation Solution
Incorporating a bilayer structure with a ferroelectric or anti-ferroelectric material for the charge blocking layer, where a second layer acts as a seed to facilitate crystallization of the first layer, enhancing crystallinity and improving the dielectric constant, thereby reducing program voltage and increasing the number of stackable layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge blocking layer is used in vertical NAND flash memory, then data retention is improved, but the crystallization difficulty leads to high program/erase voltages and small memory window
Solution Approach 1:
The patent applies composite materials by combining a ferroelectric material (first layer) with a separate layer (second layer) to form a charge blocking layer. This composite structure leverages the high dielectric constant of ferroelectric materials to reduce program/erase voltages while maintaining data retention capabilities. The specific combination of materials (e.g., HfO2 with Al2O3 or SiO2) creates synergistic effects that overcome the limitations of single-material charge blocking layers.
Solution Approach 2:
The patent changes physical parameters by controlling the crystallization state of the charge blocking layer. By inducing crystalline phases (such as orthorhombic or tetragonal phases) in the ferroelectric material through specific processing conditions, the dielectric constant is enhanced, which directly reduces the program/erase voltages required while maintaining reliable charge blocking functionality for data retention.
2Quantity of substance
If the degree of integration is increased in vertical NAND flash memory, then storage density is improved, but manufacturing complexity and process challenges increase
Solution Approach 1:
The patent segments the charge blocking layer into multiple distinct layers: a ferroelectric material layer (first layer) and a separate layer (second layer). This segmentation allows each layer to be optimized independently for its specific function, simplifying the manufacturing process by enabling separate deposition and treatment of each layer, thus reducing the overall process complexity despite high integration requirements.
Solution Approach 2:
The patent introduces an intermediary layer (second layer) between the ferroelectric material and other structures. This intermediary layer acts as a buffer or seed layer that facilitates the crystallization of the ferroelectric material and improves interface quality, thereby simplifying the manufacturing process by enabling better control over material properties without requiring complex multi-step processes.
3Power
If a ferroelectric material layer is used to reduce program voltage, then power consumption is reduced, but the crystallization difficulty remains
Solution Approach 1:
The patent introduces a second layer as an intermediary between the ferroelectric material and the surrounding structures. This intermediary layer serves as a seed layer that promotes and controls the crystallization of the ferroelectric material, ensuring consistent crystal phase formation (such as orthorhombic or tetragonal phases) without requiring complex processing conditions, thus maintaining manufacturing precision while enabling low-program voltage operation.
Solution Approach 2:
The patent applies preliminary action by depositing the second layer before or during the formation of the ferroelectric material layer. This preliminary layer is prepared in advance to provide a favorable substrate for crystallization, pre-establishing the conditions needed for controlled crystal phase formation in the ferroelectric material, thereby simplifying subsequent processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed bilayer structure reduces program/erase voltages, enhances charge storage capacity, and improves data retention by increasing the crystallinity of the charge blocking layer, leading to a more efficient and compact VNAND device design.
Implementation Method 1
a second layer configured to increase crystallization of the first layer
Implementation Method 2
a first layer including a ferroelectric material or an anti-ferroelectric material
Implementation Method 3
a first layer including a ferroelectric material or an anti-ferroelectric material
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
Provided are a vertical non-volatile memory device and an electronic apparatus including the same. The vertical non-volatile memory device includes a plurality of cell strings, each cell string of the plurality of cell strings includes a channel layer, a charge tunneling layer on the channel layer, a charge trap layer in the charge tunneling layer, a first charge blocking layer on the charge trap layer, a second charge blocking layer provided on the first charge blocking layer, and a gate electrode on the second charge blocking layer. The second charge blocking layer may include a first layer and a second layer, the first layer including a ferroelectric material or an anti-ferroelectric material, the second layer configured to facilitate crystallization of the first layer.