V-NAND Wordline Dipole Regions for Threshold Voltage Control

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Solution Overview

Problem

Existing V-NAND memory devices face challenges in maintaining consistent threshold voltages as wordline thickness decreases, particularly due to the reduction or removal of TiN barrier layers, which affects read/write operations.

Innovation Solution

Incorporating dipole regions, comprising nitride, carbide, oxide, or carbonitride of specific dipole metals with higher electronegativity than the gate metal oxide layer, adjacent to silicon oxide layers in memory stacks, to enhance threshold voltages without increasing stack thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If TiN barrier layer thickness is reduced to enable thinner wordlines, then device scaling is achieved, but threshold voltage consistency deteriorates

Engineering Contradiction:
Improvewordline thicknessVSAvoidthreshold voltage consistency
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

A dipole layer is introduced as an intermediary component between the gate metal oxide layer and the silicon oxide layer. This dipole layer, containing dipole molecules with permanent electric dipole moments, mediates the electrical interaction to maintain consistent threshold voltages even when the TiN barrier layer is thinned or removed, thus resolving the contradiction between wordline thickness reduction and threshold voltage consistency

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the electrical parameters of the gate stack by introducing a dipole layer with specific dipole moments. This alters the electric field distribution and potential profile across the interface, enabling threshold voltage control and consistency maintenance independent of the TiN barrier layer thickness

Inventive Principle:
Principle #35Parameter changes

2Volume of stationary object

If TiN barrier layer is removed to reduce stack thickness, then device density is improved, but threshold voltage control is lost

Engineering Contradiction:
Improvestack thicknessVSAvoidthreshold voltage control
Core Design Contradiction:
Volume of stationary objectVSEase of operation

Solution Approach 1:

The dipole layer serves as a functional intermediary that replaces the threshold voltage control function previously provided by the TiN barrier layer. By positioning dipole molecules at the interface between the gate metal oxide layer and silicon oxide layer, the invention maintains threshold voltage control capability without requiring the physical presence of the TiN barrier layer, thus enabling stack thinning while preserving operational control

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If wordline thickness is decreased to increase storage density, then storage capacity is improved, but read/write performance deteriorates

Engineering Contradiction:
Improvestorage densityVSAvoidread/write performance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The invention changes the electrical parameters of the gate stack by introducing a dipole layer with controlled dipole moments and orientations. This modifies the electric field strength and distribution, ensuring sufficient read/write performance even with thinner wordlines, thus resolving the contradiction between increased storage density and maintained read/write performance

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dipole regions effectively increase threshold voltages by up to 250 mV, improving resistivity and maintaining consistent performance even as TiN barrier layers decrease to zero thickness, thereby compensating for the thickness reduction and enhancing memory device functionality.

Implementation Method 1

the dipole regions comprising: a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of and a dipole metal, wherein the dipole metal comprises an electronegativity that is greater than an electronegativity of a metal of the gate metal oxide layer

Methodology Applied
Scientific EffectElectronegativity difference creating dipole moment: Electrostatics

Data Source

PatentUS11997849B2V-NAND stacks with dipole regions
Publication Date: 2024.05.28 APPLIED MATERIALS INC
  • US11997849B2 patent drawing
  • US11997849B2 patent drawing
  • US11997849B2 patent drawing

AI summary

A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.